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公开(公告)号:US20050263869A1
公开(公告)日:2005-12-01
申请号:US11138936
申请日:2005-05-25
申请人: Naotaka Tanaka , Norio Nakazato , Takahiro Naito
发明人: Naotaka Tanaka , Norio Nakazato , Takahiro Naito
IPC分类号: H01L23/12 , H01L21/56 , H01L21/60 , H01L23/31 , H01L23/48 , H01L23/485 , H01L23/495 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号: H01L23/3128 , H01L21/563 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/06181 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13144 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/83102 , H01L2224/83192 , H01L2224/92125 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要: To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip. It is possible to realize a unique connection structure having a high reliability in accordance with the caulking action using the plastic flow of a metallic bump in a very-low-cost short-TAT process and provide a three-dimensional inter-chip connection structure having a high practicability.
摘要翻译: 为了提供一种根据用于通过使用通孔电极以最短布线长度三维连接多个半导体芯片的方法来提供优异的连接可靠性的极低成本和短TAT连接结构,以便实现 紧凑,高密度和高功能的半导体系统。 通过背面研磨,半导体芯片的背面的厚度减小到规定的厚度,通过干法蚀刻,在与设备侧的外部电极部对应的后方位置形成到达表层电极的孔,金属沉积物 施加到孔的侧壁和孔的背面的周围,层叠在上侧的另一半导体芯片的金属凸块(突出电极)通过压接而变形注入到通孔中,并且金属 凸块几何地被铆接并电连接到形成在LSI芯片中的通孔的内部。 可以在非常低成本的短TAT工艺中实现使用金属凸块的塑性流动的铆接动作具有高可靠性的独特的连接结构,并且提供一种三维芯片间连接结构,其具有 实用性高。
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公开(公告)号:US06911734B2
公开(公告)日:2005-06-28
申请号:US10391746
申请日:2003-03-20
申请人: Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人: Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
CPC分类号: H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.
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公开(公告)号:US06911733B2
公开(公告)日:2005-06-28
申请号:US10372898
申请日:2003-02-26
申请人: Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人: Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
CPC分类号: H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.
摘要翻译: 来自具有布置在其两侧的表面层信号引线和表面层GND引线的带状线段的高频信号经由封装衬底的信号表面层布线直接输入到半导体芯片,并通过焊料凸块电极 。 或者,来自半导体芯片的高频信号经由带状线路部分反向输出到外部。 由于仅在封装衬底的整个表面层处的微带线传输高频信号,所以高频信号可以仅通过表层的微带线传输,而不需要通过通孔等。 因此,可以不损失频率特性来发送高频信号,并且可以在高频率传输时以低损耗的方式发送高质量的高频信号。
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公开(公告)号:US08106518B2
公开(公告)日:2012-01-31
申请号:US12640766
申请日:2009-12-17
IPC分类号: H01L23/48 , H01L23/52 , H01L29/40 , H01L21/4763
CPC分类号: H01L25/0657 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/5386 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/81 , H01L24/94 , H01L25/074 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/05557 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/1147 , H01L2224/11472 , H01L2224/13009 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13021 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/16058 , H01L2224/16112 , H01L2224/16146 , H01L2224/274 , H01L2224/81136 , H01L2224/81345 , H01L2224/81365 , H01L2224/81801 , H01L2224/81898 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/1205 , H01L2924/1306 , H01L2924/14 , H01L2924/1451 , H01L2924/19041 , H01L2924/30107 , H01L2924/35121 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
摘要翻译: 在层叠多个半导体芯片的半导体装置中,不会降低生产率而提高性能。 半导体器件具有多个元件,层间绝缘膜,焊盘和与依次形成在硅基板的主表面上的焊盘电连接的凸块电极,并且具有形成在硅衬底的背面上的背面电极 硅基板并与凸块电极电连接。 凸块电极具有贯穿焊盘并朝向硅衬底侧突出的突出部分。 背面电极形成为从硅衬底的背面侧朝向主面侧到达突起电极的突出部,并覆盖未到达的背面电极孔部的内部 垫,使得背面电极与凸块电极电连接。
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公开(公告)号:US20090014843A1
公开(公告)日:2009-01-15
申请号:US12133828
申请日:2008-06-05
IPC分类号: H01L23/52 , H01L21/60 , H01L21/4763
CPC分类号: H01L21/76898 , H01L21/6835 , H01L24/05 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/05025 , H01L2224/05553 , H01L2224/0557 , H01L2224/05572 , H01L2224/1134 , H01L2224/13025 , H01L2224/13099 , H01L2224/16147 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/90 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00013 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/14 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.
摘要翻译: 形成从半导体衬底的第二表面到达焊盘的通硅。 贯穿硅通孔中的穿透空间由直径小于第一孔直径的第一孔和第二孔形成。 第一孔由半导体衬底的第二表面到层间绝缘膜的中间形成。 此外,形成从第一孔的底部到达垫的第二孔。 然后,形成在半导体衬底的第一表面上的层间绝缘膜具有反映第一孔的底表面和半导体衬底的第一表面之间的台阶差的台阶形状。 更具体地说,第一孔的底表面和垫之间的层间绝缘膜的厚度小于其它部分的厚度。
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6.
公开(公告)号:US20050029673A1
公开(公告)日:2005-02-10
申请号:US10941570
申请日:2004-09-14
申请人: Yasuhiro Naka , Naotaka Tanaka , Ikuo Yoshida , Satoshi Imasu , Takahiro Naito
发明人: Yasuhiro Naka , Naotaka Tanaka , Ikuo Yoshida , Satoshi Imasu , Takahiro Naito
IPC分类号: H01L25/10 , H01L21/304 , H01L21/56 , H01L23/12 , H01L23/36 , H01L23/538 , H01L23/552 , H01L25/18 , H01L23/52
CPC分类号: H01L23/538 , H01L21/563 , H01L23/36 , H01L23/552 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/15311 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.
摘要翻译: 在多芯片模块型半导体器件中,第一和第二半导体元件,每个半导体元件的主要部件是半导体材料,用于在每个半导体元件中形成半导体电路,安装在电连接到 衬底,其适于安装在母板上并与母板电连接,使得每个半导体元件通过衬底电连接到母板。
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公开(公告)号:US08816506B2
公开(公告)日:2014-08-26
申请号:US13340165
申请日:2011-12-29
CPC分类号: H01L25/0657 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/5386 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/81 , H01L24/94 , H01L25/074 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/05557 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/1147 , H01L2224/11472 , H01L2224/13009 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13021 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/16058 , H01L2224/16112 , H01L2224/16146 , H01L2224/274 , H01L2224/81136 , H01L2224/81345 , H01L2224/81365 , H01L2224/81801 , H01L2224/81898 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/1205 , H01L2924/1306 , H01L2924/14 , H01L2924/1451 , H01L2924/19041 , H01L2924/30107 , H01L2924/35121 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
摘要翻译: 在层叠多个半导体芯片的半导体装置中,不会降低生产率而提高性能。 半导体器件具有多个元件,层间绝缘膜,焊盘和与依次形成在硅基板的主表面上的焊盘电连接的凸块电极,并且具有形成在硅衬底的背面上的背面电极 硅基板并与凸块电极电连接。 凸块电极具有贯穿焊盘并朝向硅衬底侧突出的突出部分。 背面电极形成为从硅衬底的背面侧朝向主面侧到达突起电极的突出部,并覆盖未到达的背面电极孔部的内侧 垫,使得背面电极与凸块电极电连接。
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公开(公告)号:US08178977B2
公开(公告)日:2012-05-15
申请号:US12483751
申请日:2009-06-12
CPC分类号: H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05025 , H01L2224/05144 , H01L2224/05155 , H01L2224/05553 , H01L2224/0557 , H01L2224/05572 , H01L2224/1134 , H01L2224/13025 , H01L2224/13099 , H01L2224/81136 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/30107 , H01L2924/00014 , H01L2224/05552
摘要: When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This causes the air leakage when the chip is sucked, and therefore, the reduction of the sucking force of the chip occurs. A concave portion is formed in advance in a region where a rear-surface wiring pad and a rear-surface wire are formed. The rear-surface wiring pad and the rear-surface wire are provided inside the concave portion. Thus, a flatness of the rear surface of the chip is ensured by a convex portion caused by thicknesses of the rear-surface wiring pad and the rear-surface wire, so that the reduction of the sucking force does not occur when the chip is handled.
摘要翻译: 当在芯片的后表面上形成通孔电极和后表面线时,由于作为通孔的一部分的后表面布线板,在芯片的后表面上形成凸部, 孔电极和后表面电线。 这导致当芯片被吸入时的空气泄漏,因此发生芯片的吸力的降低。 预先在形成背面布线衬垫和背面导线的区域中形成凹部。 后表面布线板和后表面布线设置在凹部内。 因此,通过由背面布线衬垫和后表面线的厚度引起的凸部来确保芯片的后表面的平坦度,使得当处理芯片时不会发生吸力的降低 。
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9.
公开(公告)号:US20090189256A1
公开(公告)日:2009-07-30
申请号:US12360466
申请日:2009-01-27
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: H01L24/16 , H01L21/6835 , H01L21/7682 , H01L21/76898 , H01L23/481 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/1134 , H01L2224/13025 , H01L2224/13099 , H01L2224/16145 , H01L2224/16147 , H01L2224/16225 , H01L2224/16237 , H01L2224/73204 , H01L2224/81141 , H01L2224/81191 , H01L2224/838 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00012 , H01L2224/05552
摘要: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.
摘要翻译: 在形成从其后表面侧穿过半导体衬底的环形沟槽形成并在沟槽内部和半导体衬底的后表面上形成绝缘膜之后,在绝缘膜和半导体衬底上形成通孔 从后表面侧的环形沟槽的内侧,露出在通孔的底部形成在半导体衬底的前表面上的表面保护绝缘膜。 在去除通孔底部的表面保护绝缘膜以形成露出元件表面电极的开口之后,在通孔和开口的内壁上形成连接到元件表面电极的接触电极,并且焊盘电极 由与所述接触电极相同的层形成在所述半导体衬底的后表面上。
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公开(公告)号:US20080248611A1
公开(公告)日:2008-10-09
申请号:US12037984
申请日:2008-02-27
IPC分类号: H01L21/60
CPC分类号: H01L24/11 , H01L21/563 , H01L23/3128 , H01L24/12 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/16 , H01L2224/16235 , H01L2224/73203 , H01L2224/81136 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/3511 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要: The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on the first semiconductor chip, and a sealing body are comprised. A first gold bump is connected to the wiring substrate, heating, and injection by pressure welding of the first gold bump is done under normal temperature after that at the hole-like electrode of the first semiconductor chip. Since injection by pressure welding of the second gold bump of the second semiconductor chip is done under normal temperature into the hole-like electrode of the first semiconductor chip and the second semiconductor chip is stacked, the chip-stack can be performed under normal temperature. The chip after the second stage can be stacked in the state where there is no warp in the first stage chip, by this, and the quality and reliability of the semiconductor device (semiconductor package) can be improved.
摘要翻译: 可以通过消除芯片翘曲和执行芯片堆叠来提高半导体器件的质量和可靠性。 布线基板,经由布线基板上的第一金凸块连接的第一半导体芯片,经由第一半导体芯片上的第二金凸块堆叠的第二半导体芯片和密封体。 第一金凸块连接到布线基板,通过第一金凸块的压焊进行加热和注入,在第一半导体芯片的孔状电极之后的常温下进行。 由于通过第二半导体芯片的第二金凸块的压焊而进行的注入是在常温下进入第一半导体芯片的孔状电极而第二半导体芯片堆叠的,所以可以在常温下进行芯片堆叠。 由此,可以在第一级芯片中没有翘曲的状态下堆叠第二级之后的芯片,并且可以提高半导体器件(半导体封装)的质量和可靠性。
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