公开(公告)号：US20130119562A1

公开(公告)日：2013-05-16

申请号：US13667504

申请日：2012-11-02

申请人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Osamu Inoue

发明人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Osamu Inoue

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/186 ,  H05K3/4682 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a semiconductor chip, a first insulating layer formed to cover the semiconductor chip, a wiring structure formed on the first insulating layer. The wiring structure has an alternately layered configuration including wiring layers electrically connected to the semiconductor chip and interlayer insulating layers each located between one of the wiring layers and another. The interlayer insulating layers include an outermost interlayer insulating layer located farthest from a surface of the first insulating layer. A groove formed in the outermost interlayer insulating layer passes through the outermost interlayer insulating layer in a thickness direction.

摘要翻译： 半导体封装包括半导体芯片，形成为覆盖半导体芯片的第一绝缘层，形成在第一绝缘层上的布线结构。 布线结构具有包括电连接到半导体芯片的布线层和各自位于一个布线层与另一布线层之间的层间绝缘层的交替层叠结构。 层间绝缘层包括位于距离第一绝缘层的表面最远的最外层间绝缘层。 形成在最外层间绝缘层中的沟槽沿厚度方向穿过最外层间绝缘层。

公开(公告)号：US20050253248A1

公开(公告)日：2005-11-17

申请号：US11128813

申请日：2005-05-13

申请人： Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Akio Rokugawa ,  Takahiro Iijima

发明人： Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Akio Rokugawa ,  Takahiro Iijima

IPC分类号： H05K3/46 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H01L29/76 ,  H05K1/16

CPC分类号： H01L24/81 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2203/135 ,  H01L2924/00

摘要： A multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring structure is disclosed. The multilayer wiring substrate includes a dielectric layer including a resin material mixed with an inorganic filler, wherein the inorganic filler is fabricated by mixing a paraelectric filler with an inorganic filler having a high dielectric constant.

摘要翻译： 公开了一种用于在多层布线结构内提供电容器结构的多层布线基板。 多层布线基板包括具有与无机填料混合的树脂材料的电介质层，其中无机填料是通过将正电介质填料与具有高介电常数的无机填料混合来制造的。

公开(公告)号：US06884655B2

公开(公告)日：2005-04-26

申请号：US10709912

申请日：2004-06-04

申请人： Takahiro Iljima ,  Akio Rokugawa ,  Noriyoshi Shimizu

发明人： Takahiro Iljima ,  Akio Rokugawa ,  Noriyoshi Shimizu

IPC分类号： H05K3/46 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H01L23/64 ,  H05K1/16 ,  H01L21/44 ,  H01L21/50

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  Y10S428/901

摘要： A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.

摘要翻译： 形成用作在绝缘基底构件上以预定形状图案化的电容器部分的第一电极层的布线层。 使用电泳工艺在布线层的表面上形成用作电容器部分的介电层的树脂层。 形成另一布线层，用于通过在包括树脂层的绝缘基底上进行图案化而以预定形状图案化的电容器部分的第二电极层。

公开(公告)号：US08581421B2

公开(公告)日：2013-11-12

申请号：US13328529

申请日：2011-12-16

申请人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Hirokazu Yoshino

发明人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Hirokazu Yoshino

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81192 ,  H01L2225/1035 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

摘要： According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.

摘要翻译： 根据一个实施例，提供了利用其中第一层堆叠在第二层上的支撑体的半导体封装制造方法，该方法包括：第一步骤，在第一层中形成开口以暴露第二层， ; 通过所述开口将半导体芯片布置在所述第二层上的第二步骤; 在第一层上形成树脂部分以覆盖半导体芯片的第三步骤; 以及在所述树脂部分上形成布线结构以便电连接到所述半导体芯片的第四步骤。

公开(公告)号：US07314780B2

公开(公告)日：2008-01-01

申请号：US11145924

申请日：2005-06-07

申请人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

发明人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

IPC分类号： H01L23/48

CPC分类号： H05K1/162 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  H01L2224/05599

摘要： A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.

摘要翻译： 一种半导体封装，其具有多层互连结构，用于将半导体芯片安装在其顶表面上，其中所述多层互连结构的最上层堆叠结构包括电容器结构，所述电容器结构具有介电层，所述电介质层由混合电沉积层 高介电常数无机填料和绝缘树脂，并且包括用于直接连接具有半导体芯片电极的顶电极和底电极的芯片连接焊盘，从而可以确保互连图案设计的更大自由度，电容器和半导体芯片的接近程度 可以大大改善，并且可以使包装重量更小更轻，其制造方法以及使用该半导体封装的半导体器件。

公开(公告)号：US20060131069A1

公开(公告)日：2006-06-22

申请号：US11311568

申请日：2005-12-19

申请人： Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Kiyoshi Oi ,  Akio Rokugawa

发明人： Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Kiyoshi Oi ,  Akio Rokugawa

IPC分类号： H05K1/16

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/025 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： The present invention discloses a method of manufacturing a wiring substrate to which a semiconductor chip mounted. The method includes the steps of forming a base, forming a peeling layer on the base, forming a capacitor having a plurality of layers on the peeling layer, and forming a wiring part in the capacitor for connecting the capacitor to the semiconductor chip.

公开(公告)号：US20050263874A1

公开(公告)日：2005-12-01

申请号：US11145924

申请日：2005-06-07

申请人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

发明人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

IPC分类号： H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K1/16 ,  H05K3/46 ,  H01L21/50 ,  H01L23/58

CPC分类号： H05K1/162 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  H01L2224/05599

摘要： A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.

摘要翻译： 一种半导体封装，其具有多层互连结构，用于将半导体芯片安装在其顶表面上，其中所述多层互连结构的最上层堆叠结构包括电容器结构，所述电容器结构具有介电层，所述电介质层由混合电沉积层 高介电常数无机填料和绝缘树脂，并且包括用于直接连接具有半导体芯片电极的顶电极和底电极的芯片连接焊盘，从而可以确保互连图案设计的更大自由度，电容器和半导体芯片的接近程度 可以大大改善，并且可以使包装重量更小更轻，其制造方法以及使用该半导体封装的半导体器件。

公开(公告)号：US07352060B2

公开(公告)日：2008-04-01

申请号：US11128813

申请日：2005-05-13

申请人： Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Akio Rokugawa ,  Takahiro Iijima

发明人： Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Akio Rokugawa ,  Takahiro Iijima

IPC分类号： H01L29/76 ,  H01L29/66

CPC分类号： H01L24/81 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2203/135 ,  H01L2924/00

摘要： A multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring structure is disclosed. The multilayer wiring substrate includes a dielectric layer including a resin material mixed with an inorganic filler, wherein the inorganic filler is fabricated by mixing a paraelectric filler with an inorganic filler having a high dielectric constant.

摘要翻译： 公开了一种用于在多层布线结构内提供电容器结构的多层布线基板。 多层布线基板包括具有与无机填料混合的树脂材料的电介质层，其中无机填料是通过将正电介质填料与具有高介电常数的无机填料混合来制造的。

公开(公告)号：US06921977B2

公开(公告)日：2005-07-26

申请号：US10647386

申请日：2003-08-26

申请人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

发明人： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

IPC分类号： H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K1/16 ,  H05K3/46 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/162 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  H01L2224/05599

摘要： A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.

公开(公告)号：US06828224B2

公开(公告)日：2004-12-07

申请号：US10194326

申请日：2002-07-15

申请人： Takahiro Iijima ,  Akio Rokugawa ,  Noriyoshi Shimizu

发明人： Takahiro Iijima ,  Akio Rokugawa ,  Noriyoshi Shimizu

IPC分类号： H01L214763

CPC分类号： H05K3/445 ,  H01L21/4857 ,  H01L21/486 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/056 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/423 ,  H05K3/44 ,  H05K3/4608 ,  H05K2201/0209 ,  H05K2201/09554 ,  H05K2203/135

摘要： In a process of manufacturing a core substrate of a semiconductor package using a metal core, through holes are formed in required positions on the metal core by an etching or a punching. Then, surfaces of the metal core inclusive of inner walls of the through holes are filled with insulative resin by an electrophoretic deposition process so as to form resin films. Thereafter, conductive thin films are formed on the entire surfaces of the resin films and the insides of the through holes are filled with a conductive material.

摘要翻译： 在使用金属芯制造半导体封装的芯基板的过程中，通过蚀刻或冲压在金属芯上的所需位置形成通孔。 然后，通过电泳沉积工艺，用绝缘树脂填充包括通孔内壁的金属芯的表面，以形成树脂膜。 此后，在树脂膜的整个表面上形成导电薄膜，并且用导电材料填充通孔的内部。