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1.发明申请公开(公告)号：US20160112018A1
公开(公告)日：2016-04-21
申请号：US14518967
申请日：2014-10-20
Applicant: QUALCOMM Incorporated
Inventor： Antonino Scuderi , Aristotele Hadjichristos
CPC classification number: H03F3/19 , H03F1/223 , H03F1/56 , H03F3/193 , H03F3/211 , H03F3/245 , H03F3/72 , H03F2200/18 , H03F2200/222 , H03F2200/231 , H03F2200/234 , H03F2200/249 , H03F2200/252 , H03F2200/321 , H03F2200/366 , H03F2200/387 , H03F2200/411 , H03F2200/42 , H03F2200/432 , H03F2200/451 , H03F2200/522 , H03F2200/555 , H03F2200/61 , H03F2200/75 , H03F2203/21106 , H03F2203/21136 , H03F2203/21139 , H03F2203/21142 , H03F2203/21178 , H03F2203/7215 , H03F2203/7236 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G3/007 , H03G3/3042
Abstract: In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.
Abstract translation: 在一个实施例中，本公开包括电路，该电路包括具有用于接收输入信号的输入的第一功率放大器级，耦合到输出节点的输出，第一功率放大器级接收时变电源电压。 电路还包括与第一功率放大器并联配置的第二功率放大器级，其具有用于接收输入信号的输入，耦合到输出节点的输出，第二功率放大器级接收时变电源电压。 当电源电压处于第一低电压范围时，第一功率放大器级的第一增益减小，并且第二功率放大器级的第二增益补偿第一低功率放大器级在第一低电压范围内的增益减小 。
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公开(公告)号：US09166534B2
公开(公告)日：2015-10-20
申请号：US14109239
申请日：2013-12-17
Applicant: QUALCOMM Incorporated
Inventor： Aristotele Hadjichristos , Calogero Davide Presti , Babak Nejati
CPC classification number: H03F1/565 , H03F3/19 , H03F3/191 , H03F3/195 , H03F3/245 , H03F2200/111 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03F2200/417 , H03F2200/423
Abstract: A tunable loadline is disclosed. In an exemplary embodiment, an apparatus includes an amplifier configured to output an amplified signal having a selected power level and a first impedance network coupled to receive the amplified signal at an input terminal and generate a first output signal having a first power level at a first output terminal. The first impedance network being configured to load the amplified signal to convert the selected power level to the first power level. The apparatus also includes a second impedance network configured to selectively receive the first output signal and generate a second output signal having a second power level at a second output terminal. The second impedance network being configured to combine with the first impedance network to load the amplified signal to convert the selected power level to the second power level.
Abstract translation: 公开了一种可调节负载线。 在示例性实施例中，一种装置包括：放大器，被配置为输出具有选定功率电平的放大信号和耦合以在输入端接收放大信号的第一阻抗网络，并产生第一功率电平的第一输出信号 输出端子。 第一阻抗网络被配置为加载放大的信号以将所选择的功率电平转换为第一功率电平。 该装置还包括配置成选择性地接收第一输出信号并且在第二输出端产生具有第二功率电平的第二输出信号的第二阻抗网络。 第二阻抗网络被配置为与第一阻抗网络组合以加载放大的信号以将所选择的功率电平转换为第二功率电平。
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公开(公告)号：US08970307B2
公开(公告)日：2015-03-03
申请号：US13741571
申请日：2013-01-15
Applicant: QUALCOMM Incorporated
Inventor： Thomas Domenick Marra , Aristotele Hadjichristos , Nathan M Pletcher
Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.
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公开(公告)号：US08890617B2
公开(公告)日：2014-11-18
申请号：US13741592
申请日：2013-01-15
Applicant: QUALCOMM Incorporated
Inventor： Thomas Domenick Marra , Aristotele Hadjichristos , Nathan M. Pletcher
IPC: H03G3/10
Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.
Abstract translation: 描述了用于监视和控制放大器偏置电流的技术。 在示例性设计中，装置可以包括放大器和偏置电路。 放大器可以包括耦合到电感器的至少一个晶体管。 偏置电路可以为放大器中的至少一个晶体管产生至少一个偏置电压，以获得放大器的目标偏置电流。 偏置电路可以基于放大器中的电感器两端的电压或通过放大器中的至少一个晶体管中的一个形成的电流镜的电流或栅极至源极电压来产生至少一个偏置电压 放大器中的至少一个晶体管中的一个，或复制放大器的复制电路中的电压，或禁用开关模式电源的施加到放大器的电流。
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公开(公告)号：US20140266448A1
公开(公告)日：2014-09-18
申请号：US13828646
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Jeongwon Cha , Chang-Ho Lee , Woonyun Kim , Aristotele Hadjichristos , Yu Zhao
CPC classification number: H03F3/193 , H03F1/0211 , H03F1/0261 , H03F1/22 , H03F1/223 , H03F1/3205 , H03F3/21 , H03F3/2171 , H03F3/245 , H03F2200/18 , H03F2200/61
Abstract: Exemplary embodiments are related to an envelope-tracking power amplifier. A device may include a first transistor of a plurality of transistors in a stacked configuration configured to receive a supply voltage varying with an envelope of a radio-frequency (RF) input signal. The device may further include a second transistor of the plurality in the stacked configuration coupled to a reference voltage and configured to receive a dynamic bias voltage varying inversely proportional to the supply voltage.
Abstract translation: 示例性实施例涉及包络跟踪功率放大器。 器件可以包括堆叠配置中的多个晶体管的第一晶体管，其被配置为接收随着射频（RF）输入信号的包络而变化的电源电压。 器件还可包括多个堆叠配置中的第二晶体管，其耦合到参考电压并被配置为接收与电源电压成反比变化的动态偏置电压。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20140246753A1
公开(公告)日：2014-09-04
申请号：US13787219
申请日：2013-03-06
Applicant: QUALCOMM INCORPORATED
Inventor： Young K. Song , Yunseo Park , Xiaonan Zhang , Ryan D. Lane , Babak Nejati , Aristotele Hadjichristos , Xiaoming Chen
IPC: H01L23/522 , H01L23/00
CPC classification number: H01L23/5227 , H01L23/645 , H01L24/02 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/074 , H01L25/117 , H01L2224/02375 , H01L2224/0239 , H01L2224/0401 , H01L2224/05569 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2225/06513 , H01L2225/1023 , H01L2225/1058 , H01L2924/15331 , H01L2924/014 , H01L2924/00014 , H01L2924/01029 , H01L2924/00012
Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.
Abstract translation: 一些新颖特征涉及第一示例，提供了包括印刷电路板（PCB），焊球和裸片的资产的半导体器件。 PCB包括第一金属层。 该组焊球与PCB相连。 模具通过一组焊球耦合到PCB。 模具包括第二金属层和第三金属层。 PCB的第一金属层，焊球集合，管芯的第二和第三金属层被配置为在半导体器件中作为电感器工作。 在一些实施方式中，芯片还包括钝化层。 钝化层位于第二金属层和第三金属层之间。 在一些实施方案中，第二金属层位于钝化层和一组焊球之间。
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公开(公告)号：US09692392B2
公开(公告)日：2017-06-27
申请号：US13653030
申请日：2012-10-16
Applicant: QUALCOMM Incorporated
Inventor： Jose Cabanillas , Aristotele Hadjichristos , Per O Kristensen , Mohan V Puntambekar
CPC classification number: H03H11/344 , H01P1/213 , H03H7/465 , H03H11/30 , H03H2007/386 , H04B1/0458
Abstract: Techniques to implement a filter for a selected signal path by reusing a circuit component in an unselected signal path are disclosed. In an exemplary design, an apparatus includes first, second, and third circuits. The first circuit passes a first radio frequency (RF) signal to an antenna when a first signal path is selected. The second circuit passes a second RF signal to the antenna when a second signal path is selected. The third circuit is selectively coupled to the first circuit, e.g., via a switch. The first and third circuits form a filter for the second RF signal (e.g., to attenuate a harmonic of the second RF signal) when the second signal path is selected and the first signal path is unselected. The first circuit may include a series inductor, and the third circuit may include a shunt capacitor.
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8.发明授权公开(公告)号：US09245940B2
公开(公告)日：2016-01-26
申请号：US14179202
申请日：2014-02-12
Applicant: QUALCOMM Incorporated
Inventor： Young Kyu Song , Yunseo Park , Xiaonan Zhang , Ryan David Lane , Aristotele Hadjichristos
IPC: H01L27/08 , H01L49/02 , H01L23/00 , H01L23/522
CPC classification number: H01L28/10 , H01L23/3192 , H01L23/5227 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05008 , H01L2224/05147 , H01L2224/05569 , H01L2224/05572 , H01L2224/13006 , H01L2224/16225 , H01L2924/01029 , H01L2924/30107
Abstract: An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q).
Abstract translation: 晶圆级封装（WLP）上的电感器设计不需要将焊球沉淀在芯片上，因为焊球形成电感器的一部分。 电感器上的一个端子耦合到管芯，另一个端子耦合到管芯上的单个焊球，并且与电感器机械接触的剩余焊球保持电浮动。 所产生的器件具有更好的电感，直流（DC）电阻，电路板级可靠性（BLR）和品质因数（Q）。
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公开(公告)号：US20150171800A1
公开(公告)日：2015-06-18
申请号：US14109239
申请日：2013-12-17
Applicant: QUALCOMM Incorporated
Inventor： Aristotele Hadjichristos , Calogero Davide Presti , Babak Nejati
CPC classification number: H03F1/565 , H03F3/19 , H03F3/191 , H03F3/195 , H03F3/245 , H03F2200/111 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03F2200/417 , H03F2200/423
Abstract: A tunable loadline is disclosed. In an exemplary embodiment, an apparatus includes an amplifier configured to output an amplified signal having a selected power level and a first impedance network coupled to receive the amplified signal at an input terminal and generate a first output signal having a first power level at a first output terminal. The first impedance network being configured to load the amplified signal to convert the selected power level to the first power level. The apparatus also includes a second impedance network configured to selectively receive the first output signal and generate a second output signal having a second power level at a second output terminal. The second impedance network being configured to combine with the first impedance network to load the amplified signal to convert the selected power level to the second power level.
Abstract translation: 公开了一种可调节负载线。 在示例性实施例中，一种装置包括：放大器，被配置为输出具有选定功率电平的放大信号和耦合以在输入端接收放大信号的第一阻抗网络，并产生第一功率电平的第一输出信号 输出端子。 第一阻抗网络被配置为加载放大的信号以将所选择的功率电平转换为第一功率电平。 该装置还包括配置成选择性地接收第一输出信号并且在第二输出端产生具有第二功率电平的第二输出信号的第二阻抗网络。 第二阻抗网络被配置为与第一阻抗网络组合以加载放大的信号以将所选择的功率电平转换为第二功率电平。
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公开(公告)号：US08928415B2
公开(公告)日：2015-01-06
申请号：US13678923
申请日：2012-11-16
Applicant: QUALCOMM Incorporated
Inventor： Jeongwon Cha , Chang-Ho Lee , Aristotele Hadjichristos
CPC classification number: H03F1/0277 , H03F1/223 , H03F1/523 , H03F3/211 , H03F3/245 , H03F2200/61 , H03K17/102
Abstract: Techniques for providing adjustable gain in an amplifier. In an aspect, a composite amplifier having adjustable gain includes a plurality of amplifiers coupled in parallel, wherein each of the amplifiers may be turned on or off to adjust the overall gain of the composite amplifier. Each amplifier may include an input transistor and at least two cascode transistors. To turn each amplifier off, the gate voltage of a second or lowermost cascode transistor coupled to the input transistor may be grounded, and the gate voltage of a first cascode transistor coupled to the output voltage may be coupled to a first turn-off voltage to reduce the drain-to-gate voltage drop across the first cascode transistor. Further aspects provide for decoupling a capacitor coupled to the gates of the cascode transistors from AC ground when the amplifier is turned off.
Abstract translation: 在放大器中提供可调增益的技术。 在一方面，具有可调增益的复合放大器包括并联耦合的多个放大器，其中每个放大器可被导通或关断以调整复合放大器的总体增益。 每个放大器可以包括输入晶体管和至少两个共源共栅晶体管。 为了关闭每个放大器，耦合到输入晶体管的第二或最低共源共栅晶体管的栅极电压可以接地，并且耦合到输出电压的第一共源共栅晶体管的栅极电压可以耦合到第一关断电压 降低跨越第一共源共栅晶体管的漏极 - 栅极电压降。 另外的方面提供了当放大器关闭时将耦合到共源共栅晶体管的栅极的电容器与AC地耦合的去耦合。
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