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    WAFER-TO-WAFER ALIGNMENTS
    1.
    发明申请
    WAFER-TO-WAFER ALIGNMENTS 失效
    WAFER-WAFER对准

    公开(公告)号：US20070132067A1

    公开(公告)日：2007-06-14

    申请号：US11557668

    申请日：2006-11-08

    申请人： Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Stephen Luce ,  Edmund Sprogis

    发明人： Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Stephen Luce ,  Edmund Sprogis

    IPC分类号： H01L23/544

    CPC分类号： H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

    摘要翻译： 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。 第一个方向基本上平行于共同的表面。

    METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE
    7.
    发明申请
    METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
    无平面化和相关半导体器件制造被动元件的方法

    公开(公告)号：US20080054393A1

    公开(公告)日：2008-03-06

    申请号：US11928798

    申请日：2007-10-30

    申请人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

    发明人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

    IPC分类号： H01L29/00 ,  H01L21/02

    CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

    摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

    VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF
    8.
    发明申请
    VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF 有权
    使用间隔型电极的垂直平行平板电容器及其制造方法

    公开(公告)号：US20070241424A1

    公开(公告)日：2007-10-18

    申请号：US11279434

    申请日：2006-04-12

    申请人： Timothy Dalton ,  Jeffrey Gambino ,  Anthony Stamper

    发明人： Timothy Dalton ,  Jeffrey Gambino ,  Anthony Stamper

    IPC分类号： H01L29/00

    CPC分类号： H01G4/33 ,  H01G4/236 ,  H01L28/91 ,  Y10T29/435

    摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalks of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalks of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalks of the aperture is vertical and separated by a second pair of opposite sidewalks that is outward sloped.

    摘要翻译： 电容器结构使用位于电介质层内的开口依次位于衬底上。 嵌入电介质层内的一对导体互连层终止于孔的一对相对的人行道。 一对电容器板位于孔的一对相对的人行道上，并接触一对导体互连层，但不填充孔。 电容器介质层位于一对电容器板之间并填充孔。 可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。 或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的人行道是垂直的并且被向外倾斜的第二对相对的人行道分隔开时。

    VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF
    9.
    发明申请
    VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF 审中-公开
    使用间隔型电极的垂直平行平板电容器及其制造方法

    公开(公告)号：US20080047118A1

    公开(公告)日：2008-02-28

    申请号：US11924807

    申请日：2007-10-26

    申请人： Timothy Dalton ,  Jeffrey Gambino ,  Anthony Stamper

    发明人： Timothy Dalton ,  Jeffrey Gambino ,  Anthony Stamper

    IPC分类号： H01G7/00

    CPC分类号： H01G4/33 ,  H01G4/236 ,  H01L28/91 ,  Y10T29/435

    摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.

    摘要翻译： 电容器结构使用位于电介质层内的开口依次位于衬底上。 嵌入电介质层内的一对导体互连层终止于孔的一对相对的侧壁。 一对电容器板位于孔的一对相对的侧壁上，并接触一对导体互连层，但不填充孔。 电容器介质层位于一对电容器板之间并填充孔。 可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。 或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的侧壁是垂直的并且被向外倾斜的第二对相对的侧壁隔开时。