公开(公告)号：US20080127485A1

公开(公告)日：2008-06-05

申请号：US11968695

申请日：2008-01-03

申请人： Timothy W. Budell ,  Thomas P. Camino ,  Todd W. Davies ,  Ross W. Keesler ,  Steven G. Rosser ,  David B. Stone

发明人： Timothy W. Budell ,  Thomas P. Camino ,  Todd W. Davies ,  Ross W. Keesler ,  Steven G. Rosser ,  David B. Stone

IPC分类号： H05K3/20 ,  H05K3/07

CPC分类号： H05K1/0224 ,  H05K1/0253 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09672 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2203/1178 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method for forming an electrical structure. A dielectric substrate having a metal signal line therein is provided. A first metal voltage plane is laminated to a first surface of the dielectric substrate. An opening in the first metal voltage plane is formed such that a first electrically conductive strip across the opening includes an image of a first portion of the metal signal line, wherein the image of the first portion of the metal signal line projects across the opening in the first metal voltage plane. A signal current is flowed through the metal signal line, wherein the signal current is an alternating current. A return current is flowed through the first electrically conductive strip, wherein the return current includes a portion of the signal current.

摘要翻译： 一种形成电结构的方法。 提供其中具有金属信号线的电介质基片。 将第一金属电压平面层叠到电介质基板的第一表面上。 第一金属电压平面中的开口形成为使得穿过开口的第一导电条包括金属信号线的第一部分的图像，其中金属信号线的第一部分的图像跨越开口突出 第一个金属电压平面。 信号电流流过金属信号线，其中信号电流是交流电流。 返回电流流过第一导电条，其中返回电流包括信号电流的一部分。

公开(公告)号：US07351917B2

公开(公告)日：2008-04-01

申请号：US11251745

申请日：2005-10-17

申请人： Timothy W. Budell ,  Thomas P. Comino ,  Todd W. Davies ,  Ross W. Keesler ,  Steven G. Rosser ,  David B. Stone

发明人： Timothy W. Budell ,  Thomas P. Comino ,  Todd W. Davies ,  Ross W. Keesler ,  Steven G. Rosser ,  David B. Stone

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K1/0224 ,  H05K1/0253 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09672 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2203/1178 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.

摘要翻译： 一种设计的方法，结构和方法，涉及包括层叠在电介质基板上的金属电压平面的电结构。 确定在电介质层压板的制造过程中产生的排出气体的位置在何处放置。 识别金属电压平面中的有问题的开口，其高于或低于介电层压板内的对应金属信号线，使得相应的金属信号线的一部分的图像跨越有问题的开口突出。 导电条被放置在有问题的开口处，使得条带包括图像。 在制造中，提供其中具有金属信号线的电介质基片。 金属电压平面层压到电介质基片上。 金属电压平面中的开口形成为使得条带穿过开口并且包括图像。

公开(公告)号：US06977345B2

公开(公告)日：2005-12-20

申请号：US10042031

申请日：2002-01-08

申请人： Timothy W. Budell ,  Thomas P. Comino ,  Todd W. Davies ,  Ross W. Keesler ,  Steven G. Rosser ,  David B. Stone

发明人： Timothy W. Budell ,  Thomas P. Comino ,  Todd W. Davies ,  Ross W. Keesler ,  Steven G. Rosser ,  David B. Stone

IPC分类号： H05K1/02 ,  H05K1/00

CPC分类号： H05K1/0224 ,  H05K1/0253 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09672 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2203/1178 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.

摘要翻译： 一种设计的方法，结构和方法，涉及包括层叠在电介质基板上的金属电压平面的电结构。 确定在电介质层压板的制造过程中产生的排出气体的位置在何处放置。 识别金属电压平面中的有问题的开口，其高于或低于介电层压板内的对应金属信号线，使得相应的金属信号线的一部分的图像跨越有问题的开口突出。 导电条被放置在有问题的开口处，使得条带包括图像。 在制造中，提供其中具有金属信号线的电介质基片。 金属电压平面层压到电介质基片上。 金属电压平面中的开口形成为使得条带穿过开口并且包括图像。

公开(公告)号：US06538213B1

公开(公告)日：2003-03-25

申请号：US09506951

申请日：2000-02-18

申请人： Timothy F. Carden ,  Todd W. Davies ,  Ross W. Keesler ,  Robert D. Sebesta ,  David B. Stone ,  Cheryl L. Tytran-Palomaki

发明人： Timothy F. Carden ,  Todd W. Davies ,  Ross W. Keesler ,  Robert D. Sebesta ,  David B. Stone ,  Cheryl L. Tytran-Palomaki

IPC分类号： H01R1204

CPC分类号： H05K1/114 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01R4/024 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/10734

摘要： An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.

摘要翻译： 一种用于高密度集成电路芯片连接的有机集成电路芯片载体，其中提供与外部电路的电互连的接触焊盘或微孔位于第一阵列图案中，而电镀通孔或通孔位于第二阵列 模式。 这允许利用芯片载体内的布线通道，其中可以布线信号布线。

公开(公告)号：US07196908B2

公开(公告)日：2007-03-27

申请号：US10455982

申请日：2003-06-05

申请人： Timothy W. Budell ,  David B. Stone ,  Jerzy M. Zalesinski

发明人： Timothy W. Budell ,  David B. Stone ,  Jerzy M. Zalesinski

IPC分类号： H05K7/10

CPC分类号： H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15312 ,  H05K1/111 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/05599

摘要： An electronic device, including: a plurality of contacts pads on a surface of a substrate; the contacts pads spaced apart a first predetermined distance in a first direction; and the contact pads spaced apart a second predetermined distance in a second direction, the first predetermined distance different from the second predetermined distance, the first direction perpendicular to the second direction.

摘要翻译： 一种电子设备，包括：在基板的表面上的多个接触焊盘; 所述接触垫在第一方向上间隔开第一预定距离; 并且所述接触垫在第二方向上间隔开第二预定距离，所述第一预定距离不同于所述第二预定距离，所述第一方向垂直于所述第二方向。

公开(公告)号：US06793500B1

公开(公告)日：2004-09-21

申请号：US10666607

申请日：2003-09-18

申请人： Timothy W. Budell ,  Esmaeil Rahmati ,  David B. Stone ,  Jerzy M. Zalesinski

发明人： Timothy W. Budell ,  Esmaeil Rahmati ,  David B. Stone ,  Jerzy M. Zalesinski

IPC分类号： H01R1200

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15312 ,  H05K1/0224 ,  H05K1/111 ,  H05K2201/09227 ,  H05K2201/093 ,  H05K2201/09418 ,  H05K2201/09681 ,  Y02P70/611 ,  H01L2224/05599

摘要： A structure and associated method comprising contact pads on a surface of a substrate for coupling signal, power, and ground connections for an electrical device to a plurality of conductive wires on the substrate. The contact pads are formed in single lines along radial edges of sectors on the substrate. Each of the sectors comprise a predetermined angle between the radial edges of each of the sectors. The plurality of sectors collectively form a circular area. The contact pads comprise signal, power, and ground connections located at predetermined positions on the single lines along the radial edges of each of the sectors on the substrate.

摘要翻译： 一种结构和相关方法，包括在衬底的表面上的接触焊盘，用于将用于电气设备的信号，功率和接地连接耦合到衬底上的多个导电线。 接触焊盘沿着衬底上的扇区的沿边缘沿单条线形成。 每个扇区在每个扇区的径向边缘之间包括预定角度。 多个扇区共同形成圆形区域。 接触焊盘包括沿着衬底上每个扇区的径向边缘位于单个线上的预定位置处的信号，功率和接地连接。

公开(公告)号：US09057760B2

公开(公告)日：2015-06-16

申请号：US13010057

申请日：2011-01-20

申请人： Luke D. Lacroix ,  Mark C. H. Lamorey ,  Steven F. Oakland ,  Janak G. Patel ,  Kerry P. Pfarr ,  Peter Slota, Jr. ,  David B. Stone

发明人： Luke D. Lacroix ,  Mark C. H. Lamorey ,  Steven F. Oakland ,  Janak G. Patel ,  Kerry P. Pfarr ,  Peter Slota, Jr. ,  David B. Stone

IPC分类号： G01R31/02 ,  G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/2896 ,  H01L21/76895 ,  H01L22/32

摘要： Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.

摘要翻译： 本文提供了检测电路，使用和制造方法以及设计结构。 该结构包括穿过集成电路的一个或多个金属层的至少一个信号线。 电路耦合到所述至少一个信号线，其被构造为接收具有来自至少一个信号线的已知信号或来自不同电位的信号的信号，并且基于哪个信号被接收，确定是否存在 集成电路中的结构缺陷。

公开(公告)号：US08796133B2

公开(公告)日：2014-08-05

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US08756546B2

公开(公告)日：2014-06-17

申请号：US13557386

申请日：2012-07-25

申请人： Erwin B. Cohen ,  Mark C. H. Lamorey ,  Marek A. Orlowski ,  Douglas O. Powell ,  David L. Questad ,  David B. Stone ,  Paul R. Walling

发明人： Erwin B. Cohen ,  Mark C. H. Lamorey ,  Marek A. Orlowski ,  Douglas O. Powell ,  David L. Questad ,  David B. Stone ,  Paul R. Walling

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.

摘要翻译： 计算机实现的方法提供了倒装芯片封装的芯片载体的弹性模量图。 将包括芯片载体的每个层的每个垂直对准子区域的电介质和导电设计元件的设计数据建模为弹簧以提供弹性模量图。 确定芯片载体的子区域的弹性模量在芯片接合期间识别可能的机械故障位置并冷却倒装芯片封装。 将焊料凸块修改为芯片载体可以减少施加到识别的可能的机械故障位置的应力。 修改芯片载体设计以减少与识别出的可能的机械故障位置相关联的子区域的刚度，还可减少芯片连接和冷却的应力。

公开(公告)号：US20140021622A1

公开(公告)日：2014-01-23

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。