公开(公告)号：US5910685A

公开(公告)日：1999-06-08

申请号：US984330

申请日：1997-12-03

申请人： Masayuki Watanabe ,  Toshio Sugano ,  Seiichiro Tsukui ,  Takashi Ono ,  Yoshiaki Wakashima

发明人： Masayuki Watanabe ,  Toshio Sugano ,  Seiichiro Tsukui ,  Takashi Ono ,  Yoshiaki Wakashima

IPC分类号： G11C5/00 ,  H01L23/495 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G11C5/02 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/49572 ,  H01L24/16 ,  H01L24/50 ,  H01L25/0657 ,  H01L25/105 ,  H05K1/141 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K2201/10515 ,  H05K2201/10681 ,  H05K2203/1572 ,  H05K3/3447 ,  H05K3/368

摘要： In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

公开(公告)号：US5818792A

公开(公告)日：1998-10-06

申请号：US804683

申请日：1997-02-25

申请人： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

发明人： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G01C13/00

CPC分类号： G11C29/80 ,  G11C29/74 ,  G11C29/808 ,  G11C29/832

摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.

摘要翻译： 第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障 在记忆垫单位。 电源基本上被切断供给故障存储器垫。

公开(公告)号：US5198888A

公开(公告)日：1993-03-30

申请号：US631154

申请日：1990-12-20

申请人： Toshio Sugano ,  Kohji Nagaoka ,  Seiichiro Tsukui ,  Yoshiaki Wakashima ,  Michio Tanimoto ,  Masayuki Watanabe ,  Suguru Sakaguchi ,  Kunihiko Nishi ,  Aizo Kaneda ,  Kohji Serizawa ,  Michiharu Honda ,  Tohru Yoshida ,  Takeshi Komaru ,  Atsushi Nakamura

发明人： Toshio Sugano ,  Kohji Nagaoka ,  Seiichiro Tsukui ,  Yoshiaki Wakashima ,  Michio Tanimoto ,  Masayuki Watanabe ,  Suguru Sakaguchi ,  Kunihiko Nishi ,  Aizo Kaneda ,  Kohji Serizawa ,  Michiharu Honda ,  Tohru Yoshida ,  Takeshi Komaru ,  Atsushi Nakamura

IPC分类号： G11C5/00 ,  H01L23/498 ,  H01L25/065 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

CPC分类号： G11C5/06 ,  G11C5/02 ,  H01L23/49805 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06596 ,  H01L2924/07811 ,  H01L2924/09701 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3421 ,  H05K3/363

摘要： There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.

摘要翻译： 存在增加需要大容量存储器的器件的面积的趋势，其由半导体存储器占据。 这种趋势阻碍了设备尺寸的减小。 本发明旨在提供一种能够在最小化安装面积的同时具有高集成度，高密度和大容量的存储器。 为了实现这种记忆，现有技术的TAB（磁带自动接合）被安装在导电连接器上，并且由TAB和连接器组成的多个结构被堆叠。 此外，将TAB安装在其上的连接器构造成使得堆叠的TAB的独立端子可能不会短路。

公开(公告)号：US06788560B2

公开(公告)日：2004-09-07

申请号：US08806674

申请日：1997-02-26

申请人： Toshio Sugano ,  Seiichiro Tsukui ,  Kensuke Tsuneda

发明人： Toshio Sugano ,  Seiichiro Tsukui ,  Kensuke Tsuneda

IPC分类号： G11C502

CPC分类号： G11C8/14 ,  G11C5/04 ,  G11C8/10 ,  H01L2224/4826 ,  H05K1/029 ,  H05K1/181 ,  H05K3/222 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2203/173 ,  Y02P70/611

摘要： A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

摘要翻译： 一种存储模块MM，其中模块布线基板5配备有功能切换装置KK1和KK2，用于任意切换要输入到存储器1的功能切换引脚FP0和FP1的功能切换信号。通过这些功能切换装置KK1和KK2， 此外，功能切换信号从任何一个无连接，电源电压Vcc和接地电位Vss任意切换。 这些信号完全输入到所有安装的存储器1中，以切换和任意设置包括读取模式和刷新周期的功能。

公开(公告)号：US06215687B1

公开(公告)日：2001-04-10

申请号：US09512476

申请日：2000-02-24

申请人： Toshio Sugano ,  Seiichiro Tsukui ,  Kensuke Tsuneda

发明人： Toshio Sugano ,  Seiichiro Tsukui ,  Kensuke Tsuneda

IPC分类号： G11C502

CPC分类号： G11C8/14 ,  G11C5/04 ,  G11C8/10 ,  H01L2224/4826 ,  H05K1/029 ,  H05K1/181 ,  H05K3/222 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2203/173 ,  Y02P70/611

摘要： A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

公开(公告)号：US5910010A

公开(公告)日：1999-06-08

申请号：US732215

申请日：1997-02-18

申请人： Hirotaka Nishizawa ,  Tomoyoshi Miura ,  Ichirou Anjou ,  Masamichi Ishihara ,  Masahiro Yamamura ,  Sadao Morita ,  Takashi Araki ,  Kiyoshi Inoue ,  Toshio Sugano ,  Tetsuji Kohara ,  Toshio Yamada ,  Yasushi Sekine ,  Yoshiaki Anata ,  Masakatsu Goto ,  Norihiko Kasai ,  Shinobu Takeura ,  Mutsuo Tsukuda ,  Yasunori Yamaguchi ,  Jiro Sawada ,  Hidetoshi Iwai ,  Seiichiro Tsukui ,  Tadao Kaji ,  Noboru Shiozawa

发明人： Hirotaka Nishizawa ,  Tomoyoshi Miura ,  Ichirou Anjou ,  Masamichi Ishihara ,  Masahiro Yamamura ,  Sadao Morita ,  Takashi Araki ,  Kiyoshi Inoue ,  Toshio Sugano ,  Tetsuji Kohara ,  Toshio Yamada ,  Yasushi Sekine ,  Yoshiaki Anata ,  Masakatsu Goto ,  Norihiko Kasai ,  Shinobu Takeura ,  Mutsuo Tsukuda ,  Yasunori Yamaguchi ,  Jiro Sawada ,  Hidetoshi Iwai ,  Seiichiro Tsukui ,  Tadao Kaji ,  Noboru Shiozawa

IPC分类号： H01L21/56 ,  H01L21/98 ,  H01L23/495 ,  H01L25/065 ,  H01L21/52 ,  H01L21/58 ,  H01L21/60

CPC分类号： H01L24/06 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49575 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351

摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

摘要翻译： PCT No.PCT / JP95 / 00662 Sec。 371日期1997年2月18日 102（e）日期1997年2月18日PCT提交1995年4月5日PCT公布。 WO95 / 29506 PCT公开号 日期：1995年11月2日制造半导体集成电路器件的方法包括以下步骤：构造多个引线框架，引线框架各自包括内部部分和外部部分，并将半导体芯片电连接到引线的内部 每一帧。 然后将引线框架彼此堆叠以形成垂直堆叠，然后将板在每个引线框架之间插入，每个板在中心具有开口，由此在堆叠中形成中心空腔。 然后将堆叠放置在顶模构件和底模构件之间，并将树脂注入到中心腔中，由此树脂固化以形成封装半导体芯片的单个树脂封装。 然后将树脂包装从模具部件中释放出来。

公开(公告)号：US5691952A

公开(公告)日：1997-11-25

申请号：US590608

申请日：1996-01-24

申请人： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

发明人： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C29/80 ,  G11C29/74 ,  G11C29/808 ,  G11C29/832

摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.

摘要翻译： 第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障 在记忆垫单位。 电源基本上被切断供给故障存储器垫。

公开(公告)号：US4982265A

公开(公告)日：1991-01-01

申请号：US209739

申请日：1988-06-22

申请人： Masayuki Watanabe ,  Toshio Sugano ,  Seiichiro Tsukui ,  Takashi Ono ,  Yoshiaki Wakashima

发明人： Masayuki Watanabe ,  Toshio Sugano ,  Seiichiro Tsukui ,  Takashi Ono ,  Yoshiaki Wakashima

IPC分类号： G11C5/00 ,  H01L23/495 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC分类号： H05K1/141 ,  G11C5/00 ,  H01L23/49572 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1147 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/01055 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H05K2201/10515 ,  H05K2201/10681 ,  H05K2203/1572 ,  H05K3/3447 ,  H05K3/368

摘要： In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

摘要翻译： 在本发明中，存储芯片通过TAB（磁带自动键合）以堆叠的方式粘合在一起，并且由芯片和引线形成像SOP（小外线封装）的多存储器芯片和引线复合体，由此存储器 高封装密度的模块可以通过扁平封装技术实现。

公开(公告)号：US06756661B2

公开(公告)日：2004-06-29

申请号：US09800503

申请日：2001-03-08

申请人： Kensuke Tsuneda ,  Toshio Sugano ,  Seiichiro Tsukui ,  Kouji Nagaoka ,  Tomohiko Sato

发明人： Kensuke Tsuneda ,  Toshio Sugano ,  Seiichiro Tsukui ,  Kouji Nagaoka ,  Tomohiko Sato

IPC分类号： H01L23495

CPC分类号： H01L23/49811 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/50

摘要： A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

摘要翻译： 装载有四个芯片（1组16位型）的存储器TCP由一层双层布线层结构的磁带，安装在该磁带上的四个芯片等构成。公共信号端子布置在一组两个相对的 侧，另一侧设置独立的信号端子。 两侧的公共信号端子彼此电连接公共信号线。 此外，在将该存储器TCP安装到基板的前侧和后侧的DIMM中，在矩形基板的一个长边上形成有多个外部端子，并且安装存储器TCP，使得存储器的独立信号端子 沿着这些外部端子的排列方向布置TCP。

公开(公告)号：US06744656B2

公开(公告)日：2004-06-01

申请号：US10184920

申请日：2002-07-01

申请人： Toshio Sugano ,  Seiichiro Tsukui ,  Kensuke Tsuneda

发明人： Toshio Sugano ,  Seiichiro Tsukui ,  Kensuke Tsuneda

IPC分类号： G11C502

CPC分类号： G11C8/14 ,  G11C5/04 ,  G11C8/10 ,  H01L2224/4826 ,  H05K1/029 ,  H05K1/181 ,  H05K3/222 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2203/173 ,  Y02P70/611

摘要： A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.