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    Chip scale package with compliant leads
    1.
    发明授权
    Chip scale package with compliant leads 有权
    芯片级封装符合引脚

    公开(公告)号：US06900110B1

    公开(公告)日：2005-05-31

    申请号：US10318426

    申请日：2002-12-13

    申请人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

    发明人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

    IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L21/76

    CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013

    摘要： A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.

    摘要翻译： 描述了一种晶片级制造的芯片级集成电​​路封装，其具有形成在封装的集成电路管芯之间的空气间隙和位于管芯上并导电地附接于管芯的柔性引线。 柔性引线上的接触凸块偏移可提供集成电路封装与其他基板的连接。 在一些实施例中，柔性引线包括覆盖有外部弹性层的导电层，并且还可以包括导电层下面的内部弹性层。 外部弹性层具有通过其形成的通孔，其暴露下面的导电层。 通孔沿柔性引线偏离与接合焊盘的水平距离，其中顺应引线与导电耦合。 芯片尺寸封装提供了管芯与管芯所连接的任何衬底之间高度兼容的连接。

    Universal tape for integrated circuits
    2.
    发明授权
    Universal tape for integrated circuits 有权
    集成电路通用磁带

    公开(公告)号：US06398034B1

    公开(公告)日：2002-06-04

    申请号：US09515588

    申请日：2000-02-29

    申请人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

    发明人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

    IPC分类号： B65D8500

    CPC分类号： B65D73/02 ,  H05K13/0084

    摘要： The present invention provides a low cost carrier tape designed to store chips during transportation. The invention comprises a carrier tape which contains receptacle holes designed to secure chips onto the carrier tape by clasping onto the chip's electrical contacts. The receptacle holes prevent the chip from rotating and physically moving. The receptacle holes are formed in patterns to match the standardized electrical contact patterns of flip chip families. The diameters of the receptacle holes may be sized slightly smaller than the diameter of electrical contacts such that a chip is secured by “snap-fitting” each electrical contact into a receptacle hole. Relief slits may be formed on the edges of the receptacle holes to facilitate the “snap-fitting” of electrical contacts into receptacle holes.

    摘要翻译： 本发明提供了一种设计用于在运输期间存储芯片的低成本载带。 本发明包括载带，该载带包含设计成通过扣紧芯片的电触点将芯片固定到载带上的插座孔。 插座孔防止芯片旋转和物理移动。 插座孔以图案形成以匹配倒装芯片族的标准化电接触图案。 容纳孔的直径的尺寸可以略小于电触头的直径，使得芯片通过将每个电触头“卡扣配合”到插座孔中来固定。 可以在容纳孔的边缘上形成浮雕狭缝，以便于将电触点“卡扣配合”到插孔中。

    Wafer level chip scale package
    3.
    发明授权
    Wafer level chip scale package 有权
    晶圆级芯片级封装

    公开(公告)号：US07241643B1

    公开(公告)日：2007-07-10

    申请号：US11126461

    申请日：2005-05-10

    申请人： Nikhil Vishwanath Kelkar ,  Hem P. Takiar

    发明人： Nikhil Vishwanath Kelkar ,  Hem P. Takiar

    IPC分类号： H01L21/00 ,  H01L21/44

    CPC分类号： H01L23/49827 ,  H01L23/4985 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05099

    摘要： A wafer level fabricated integrated circuit package having an air gap formed between the integrated circuit die of the package and a flexible circuit film located over and conductively attached to the die though raised interconnects formed on the die is described. The flexible circuit film further includes routing conductors that connect inner landings on the bottom surface of the flexible circuit film with outer landings on the top surface of the flexible circuit film. The outer landings are offset a horizontal distance from the inner landings. In some embodiments, contact bumps are formed on the outer landings of the flexible circuit film layer for use in connecting the package to other substrates. The wafer level chip scale package provides a highly compliant connection between the die and any other substrate that the die is attached to.

    摘要翻译： 描述了一种晶片级制造的集成电路封装，其具有形成在封装的集成电路管芯之间的空气间隙和柔性电路膜，所述柔性电路膜位于通过形成在管芯上的升高的互连件并且导电地附接到管芯上。 柔性电路膜还包括将柔性电路膜的底表面上的内部平台与柔性电路膜的顶表面上的外部平台连接的布线导体。 外部着陆偏离内部平台的水平距离。 在一些实施例中，接触凸块形成在柔性电路膜层的外部平台上，用于将封装连接到其它基板。 晶片级芯片级封装提供了管芯与管芯所连接的任何其它衬底之间高度兼容的连接。

    Metal coated markings on integrated circuit devices
    4.
    发明授权
    Metal coated markings on integrated circuit devices 有权
    集成电路设备上的金属涂层标记

    公开(公告)号：US06448632B1

    公开(公告)日：2002-09-10

    申请号：US09649264

    申请日：2000-08-28

    申请人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar ,  Ken Pham

    发明人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar ,  Ken Pham

    IPC分类号： H01L23552

    CPC分类号： H01L23/544 ,  H01L23/552 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A semiconductor device comprising a mark located on a surface of the semiconductor device and a metal layer covering the marked surface and the mark. The metal layer functions to protect the semiconductor device from exposure to electromagnetic radiation and allows the mark to be visible for identification purposes. The present invention also pertains a method of manufacturing the semiconductor device as described. The method involves forming a mark on a semiconductor substrate surface of the device and covering the semiconductor substrate surface and the mark with a layer of metal so that the device is protected from exposure to electromagnetic radiation and allows the mark to be visible for identification purposes.

    摘要翻译： 一种半导体器件，包括位于半导体器件的表面上的标记和覆盖标记表面的金属层和标记。 金属层用于保护半导体器件免受电磁辐射的影响，并允许标记为了识别而可见。 本发明还涉及制造如上所述的半导体器件的方法。 该方法包括在器件的半导体衬底表面上形成标记，并用金属层覆盖半导体衬底表面和标记，使得器件免受暴露于电磁辐射的影响，并允许标记为识别目的而可见。

    Chip scale package with compliant leads
    5.
    发明授权
    Chip scale package with compliant leads 有权
    芯片级封装符合引脚

    公开(公告)号：US06521970B1

    公开(公告)日：2003-02-18

    申请号：US09653820

    申请日：2000-09-01

    申请人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

    发明人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar

    IPC分类号： H01L2900

    CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013

    摘要： A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.

    摘要翻译： 描述了一种晶片级制造的芯片级集成电​​路封装，其具有形成在封装的集成电路管芯之间的空气间隙和位于管芯上并导电地附接于管芯的柔性引线。 柔性引线上的接触凸块偏移可提供集成电路封装与其他基板的连接。 在一些实施例中，柔性引线包括覆盖有外部弹性层的导电层，并且还可以包括导电层下面的内部弹性层。 外部弹性层具有通过其形成的通孔，其暴露下面的导电层。 通孔沿柔性引线偏离与接合焊盘的水平距离，其中顺应引线与导电耦合。 芯片尺寸封装提供了管芯与管芯所连接的任何衬底之间高度兼容的连接。

    Opaque metallization to cover flip chip die surface for light sensitive semiconductor devices
    8.
    发明授权
    Opaque metallization to cover flip chip die surface for light sensitive semiconductor devices 有权
    不透明金属化以覆盖用于光敏半导体器件的倒装芯片裸片表面

    公开(公告)号：US06249044B1

    公开(公告)日：2001-06-19

    申请号：US09335440

    申请日：1999-06-17

    申请人： Pai-Hsiang Kao ,  Nikhil Vishwanath Kelkar

    发明人： Pai-Hsiang Kao ,  Nikhil Vishwanath Kelkar

    IPC分类号： H01L2900

    CPC分类号： H01L23/552 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/16 ,  H01L2924/01322 ,  H01L2924/3025

    摘要： A light shield is provided for light sensitive flip chip integrated circuits. The flip chip includes an under bump layer to portions of which solder bumps are attached. A separate portion of this under bump layer is used to provide the light shield. The light shield excludes ambient light from the most light sensitive portions of the circuit so that the electrical characteristics of the flip chip integrated circuit are not significantly altered when the flip chip is operated in ambient light.

    摘要翻译： 为光敏倒装芯片集成电路提供了一个遮光罩。 倒装芯片包括底部凸起层，其中部分焊料凸点被附着。 该凹凸层的单独部分用于提供遮光罩。 遮光罩不包括来自电路的最光敏部分的环境光，因此当倒装芯片在环境光中工作时，倒装芯片集成电路的电气特性不会明显改变。