公开(公告)号：US20240355373A1

公开(公告)日：2024-10-24

申请号：US18757528

申请日：2024-06-28

申请人： SHENZHEN PANGO MICROSYSTEMS CO.,LTD

发明人： JIN ZHANG ,  WEI DING ,  RUSHANG HUANG

IPC分类号： G11C7/22 ,  G11C7/04 ,  G11C11/4076

CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C11/4076

摘要： The present application discloses a method for adjusting phase of a DQS signal, which is applied to the field of field programmable logic gate arrays and is used to solve the temperature drift problem of the DQS signal in DDR. The method provided by the present application includes: receiving a phase adjustment instruction, and adjusting phase of the DQS signal according to a preset first adjustment rule; receiving a signal sampling instruction to sample the DQS signal, and returning a sampling result of the DQS signal; determining whether the sampling result is correct, and storing a determination result; cycling steps of receiving the phase adjustment instruction to storing the determination result until a number of cycles reaches a preset number of times; according to the determination result corresponding to the number of cycles, adjusting the phase of the DQS signal according to a preset second adjustment rule.

公开(公告)号：US12127391B2

公开(公告)日：2024-10-22

申请号：US18458054

申请日：2023-08-29

申请人： Kioxia Corporation

发明人： Teruhisa Sonohara ,  Shunichi Seno ,  Hiroki Tokuhira ,  Fumitaka Arai

IPC分类号： G11C11/24 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC分类号： H10B12/30 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  H01L21/02565 ,  H01L29/66969 ,  H01L29/7869 ,  H10B12/03 ,  H10B12/05

摘要： A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

公开(公告)号：US12119049B2

公开(公告)日：2024-10-15

申请号：US18490042

申请日：2023-10-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC分类号： G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C7/14 ,  G11C11/4093

CPC分类号： G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

摘要： A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US12112790B2

公开(公告)日：2024-10-08

申请号：US17847031

申请日：2022-06-22

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shu-Wei Yang

IPC分类号： G06F1/10 ,  G11C11/4076 ,  H03L7/081

CPC分类号： G11C11/4076 ,  H03L7/0816

摘要： A method for determining a target locking time for a delay locked loop of a memory apparatus are provided. The method includes, a system inputting a first set of input signals to the memory apparatus in accordance with a first set of first operational parameters and a set of second operational parameters, the system measuring a first set of output signals from the memory apparatus in response to the first set of input signals to determine whether the delay locked loop fails at any combination of the first set of first operational parameters and the set of second operational parameters, the system determining a first candidate operational parameter from the first set of first operational parameters under which the delay locked loop does not fail for each of the set of second operational parameters, and the system determining the target locking time based on the first candidate operational parameter.

公开(公告)号：US20240331757A1

公开(公告)日：2024-10-03

申请号：US18740242

申请日：2024-06-11

申请人： Micron Technology, Inc.

发明人： Hari Giduturi

IPC分类号： G11C11/4076 ,  G11C5/04 ,  G11C5/06 ,  H01L25/065

CPC分类号： G11C11/4076 ,  G11C5/06 ,  H01L25/0657 ,  G11C5/04 ,  H01L2225/06506 ,  H01L2225/06562

摘要： A packaged memory device can include a primary memory die coupled to a shared intra-package communication bus and coupled to an external host device using a host interface bus, and the host interface bus can include a host clock channel. The memory device can include multiple secondary dies coupled to the intra-package communication bus, and each of the secondary dies can be configured to receive the same messages from the primary memory die using the intra-package communication bus. The primary memory die can send a first message to, or receive a first message from, a particular one of the secondary dies using the intra-package communication bus, and the first message can include a first chip identification field that exclusively indicates the particular one of the secondary dies.

公开(公告)号：US12106794B2

公开(公告)日：2024-10-01

申请号：US18330527

申请日：2023-06-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC分类号： G11C11/40 ,  G06F3/06 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

CPC分类号： G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20240312511A1

公开(公告)日：2024-09-19

申请号：US18183177

申请日：2023-03-14

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Takeo Okamoto

IPC分类号： G11C11/4076 ,  H10B80/00

CPC分类号： G11C11/4076 ,  H10B80/00

摘要： A stacked memory with a timing adjustment function is provided, including a logic chip; a memory chip coupled to the logic chip in a face-to-face manner and including plural memory tiles; plural timing adjustment devices, respectively provided in each memory tile, wherein for each memory tile, each timing adjustment device further includes a first timing adjustment device that is configured to adjust setup times and hold times for a command and an address with respect to an edge of a clock signal and a second timing adjustment device that is configured to adjust a setup time and a hold time for input data with respect to the edge of the clock signal.

公开(公告)号：US20240312509A1

公开(公告)日：2024-09-19

申请号：US18507901

申请日：2023-11-13

申请人： SK hynix Inc.

发明人： Choung Ki SONG

IPC分类号： G11C11/4072 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093 ,  H01L23/00 ,  H01L25/18 ,  H10B80/00

CPC分类号： G11C11/4072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4093 ,  H01L24/48 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/48091 ,  H01L2224/48227

摘要： A buffer chip may include: a chip select signal reception circuit configured to receive system chip select signals transmitted from a memory controller; a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information; and a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips.

公开(公告)号：US20240290379A1

公开(公告)日：2024-08-29

申请号：US18656156

申请日：2024-05-06

申请人： Micron Technology, Inc.

发明人： Riccardo Pazzocco ,  Angelo Visconti

IPC分类号： G11C11/4096 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC分类号： G11C11/4096 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093

摘要： Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

公开(公告)号：US20240289047A1

公开(公告)日：2024-08-29

申请号：US18412731

申请日：2024-01-15

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC分类号： G06F3/06 ,  G06F13/16 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/065

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/06 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/0657 ,  G06F2213/16 ,  G11C7/1015 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L2225/06541

摘要： First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.