公开(公告)号：WO2017052604A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052288

申请日：2015-09-25

Applicant: INTEL CORPORATION ,  LILAK, Aaron D. ,  MORROW, Patrick ,  CEA, Stephen M. ,  MEHANDRU, Rishabh ,  WEBER, Cory E.

Inventor： LILAK, Aaron D. ,  MORROW, Patrick ,  CEA, Stephen M. ,  MEHANDRU, Rishabh ,  WEBER, Cory E.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/26506 ,  H01L29/785

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

Abstract translation: 本发明的实施例涉及在三栅极或Fin-FET器件中形成具有不同有源沟道高度的翅片。 在一个实施例中，至少两个翅片形成在基板的正面上。 栅极结构在鳍的至少一部分的顶表面和一对侧壁上延伸。 在一个实施例中，将基板变薄以暴露翅片的底表面。 接下来，可以在每个鳍上执行背面蚀刻以形成有源沟道区。 翅片可以凹入到不同的深度，形成具有不同高度的有源通道区域。

公开(公告)号：WO2017052562A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052033

申请日：2015-09-24

Applicant: INTEL CORPORATION ,  MORROW, Patrick ,  KOBRINSKY, Mauro J. ,  JUN, Kimin ,  SON, Il-Seok ,  FISCHER, Paul B.

Inventor： MORROW, Patrick ,  KOBRINSKY, Mauro J. ,  JUN, Kimin ,  SON, Il-Seok ,  FISCHER, Paul B.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/41791 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

Abstract translation: 描述了由此形成的方法和结构，用于形成用于微电子器件的自对准接触结构。 实施例包括在设置在器件层中的晶体管器件的源极/漏极区域中形成沟槽，其中器件层位于衬底上，在沟槽中形成填充材料，在填充材料上形成源极/漏极材料， 在源极/漏极材料的第一侧上形成第一源极/漏极接触，然后在源极/漏极材料的第二侧上形成第二源极漏极接触。

公开(公告)号：WO2011126925A2

公开(公告)日：2011-10-13

申请号：PCT/US2011030808

申请日：2011-03-31

Applicant: INTEL CORP ,  MA QING ,  HE JUN ,  MORROW PATRICK ,  FISCHER PAUL B ,  BALAKRISHNAN SRIDHAR ,  RADHAKRISHNAN SATISH ,  ANDRYUSHCHENKO TATYANA TANYA ,  XU GUANGHAI

Inventor： MA QING ,  HE JUN ,  MORROW PATRICK ,  FISCHER PAUL B ,  BALAKRISHNAN SRIDHAR ,  RADHAKRISHNAN SATISH ,  ANDRYUSHCHENKO TATYANA TANYA ,  XU GUANGHAI

IPC: H05K3/32 ,  H05K1/18

CPC classification number: H01L24/19 ,  B23K1/0016 ,  H01L21/0334 ,  H01L24/11 ,  H01L2224/245 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/4015 ,  H05K2201/1028 ,  H01L2924/00

Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

Abstract translation: 本主题涉及制造微电子器件的领域。 在至少一个实施例中，本主题涉及形成具有其部分的互连，其在附接到外部设备之后在冷却期间从微电子器件脱粘。 脱粘部分允许互连件弯曲并吸收应力。

公开(公告)号：WO2011084216A2

公开(公告)日：2011-07-14

申请号：PCT/US2010/054931

申请日：2010-11-01

Applicant: INTEL CORPORATION ,  MA, Qing ,  HU, Chuan ,  MORROW, Patrick

Inventor： MA, Qing ,  HU, Chuan ,  MORROW, Patrick

IPC: H01L23/485 ,  H05K3/46

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的基板的实施例。 衬底包括由已经结合在一起的两个或更多个离散的玻璃层组成的芯。 可以在相邻的玻璃层之间设置单独的粘合层，以将这些层连接在一起。 衬底还可以包括在多层玻璃芯的相对侧上或者可能在芯的一侧上的堆积结构。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸通过多层玻璃芯，并且一个或多个导体可以与布置在芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：WO2016204755A1

公开(公告)日：2016-12-22

申请号：PCT/US2015/036286

申请日：2015-06-17

Applicant: INTEL CORPORATION ,  MEHANDRU, Rishabh ,  MORROW, Patrick ,  KUMAR, Ranjith ,  WEBER, Cory, E. ,  KIM, Seiyon ,  CEA, Stephen, M. ,  GHANI, Tahir

Inventor： MEHANDRU, Rishabh ,  MORROW, Patrick ,  KUMAR, Ranjith ,  WEBER, Cory, E. ,  KIM, Seiyon ,  CEA, Stephen, M. ,  GHANI, Tahir

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1211 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

Abstract translation: 描述用于半导体器件的区域缩放的垂直集成方案和电路元件架构。 在一个示例中，逆变器结构包括垂直分离成上部区域和下部区域的半导体鳍片。 包括用于控制半导体鳍片的上部区域的第一多个栅极结构。 包括第二多个栅极结构以控制半导体鳍片的下部区域。 第二多个栅极结构具有与第一多个栅极结构的导电类型相反的导电类型。

公开(公告)号：WO2016195664A1

公开(公告)日：2016-12-08

申请号：PCT/US2015/033757

申请日：2015-06-02

Applicant: INTEL CORPORATION ,  WANG, Yih ,  MORROW, Patrick

Inventor： WANG, Yih ,  MORROW, Patrick

IPC: G11C13/00

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233

Abstract: A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.

Abstract translation: 具有形成在基板的背面上的金属化层的微电子存储器，其中背侧上的金属化层可用于形成源极线和字线。 这样的配置可以允许减少位单元面积，更高的存储器阵列密度以及较低的源极线和字线电阻。 此外，这种配置还可以提供独立地优化逻辑和存储器电路的互连性能的灵活性。

公开(公告)号：WO2015195084A1

公开(公告)日：2015-12-23

申请号：PCT/US2014/042577

申请日：2014-06-16

Applicant: INTEL CORPORATION ,  NELSON, Donald W. ,  WEBB, M Clair ,  MORROW, Patrick ,  JUN, Kimin

Inventor： NELSON, Donald W. ,  WEBB, M Clair ,  MORROW, Patrick ,  JUN, Kimin

IPC: H01L21/335 ,  H01L29/78

CPC classification number: H01L43/02 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0694 ,  H01L27/101 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2224/03 ,  H01L2924/014

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.

Abstract translation: 一种方法，包括在包括多个电路装置的集成电路装置层的相对侧上形成多个第一互连和多个第二互连，其中形成多个第一互连中的一个和多个第二互连包括嵌入存储器件 在其中。 一种装置，包括在包括多个电路装置的集成电路装置层的相对侧上包括多个第一互连和多个第二互连的基板，其中多个第一互连和多个第二互连中的一个包括存储装置 嵌入其中。

公开(公告)号：WO2015191088A1

公开(公告)日：2015-12-17

申请号：PCT/US2014/042389

申请日：2014-06-13

Applicant: INTEL CORPORATION ,  JUN, Kimin ,  DASGUPTA, Sansaptak ,  LEVANDER, Alejandro, X. ,  MORROW, Patrick

Inventor： JUN, Kimin ,  DASGUPTA, Sansaptak ,  LEVANDER, Alejandro, X. ,  MORROW, Patrick

IPC: H01L29/778

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

Abstract translation: 一种包括在牺牲基板上的极性化合物半导体层上形成阻挡层的方法; 将牺牲衬底耦合到载体衬底以形成其中阻挡层设置在极性化合物半导体层和载体衬底之间的复合结构; 将牺牲衬底与复合结构分离以暴露极化合物半导体层; 以及形成至少一个电路装置。 一种在基板上包括阻挡层的装置; 阻挡层上的晶体管器件; 以及设置在所述阻挡层和所述晶体管器件之间的极性化合物半导体层，所述极性化合物半导体层包含二维电子气。

公开(公告)号：WO2014209278A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/047542

申请日：2013-06-25

Applicant: INTEL CORPORATION ,  MORROW, Patrick ,  JUN, Kimin ,  WEBB, M. Clair ,  NELSON, Donald W.

Inventor： MORROW, Patrick ,  JUN, Kimin ,  WEBB, M. Clair ,  NELSON, Donald W.

IPC: H01L21/768 ,  H01L27/105 ,  H01L21/28

CPC classification number: H01L27/0688 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

Abstract translation: 使用一个或多个本地级间互连的单片3D IC，其与3D IC内的至少一个晶体管级上的至少一个晶体管的至少一个结构紧密集成。 在某些实施例中，局部级间互连与至少一个晶体管的栅电极或源/漏区相交，并延伸穿过设置在3D IC中的第一和第二晶体管级之间的至少一个级间介质层。 有利地，本地级间互连可以在3D IC的不同级别中的晶体管之间进行直接垂直连接，而不会横向绕过互连的上覆或下伏晶体管级的覆盖区（即，横向或平面区域）。

公开(公告)号：WO2014159980A2

公开(公告)日：2014-10-02

申请号：PCT/US2014/025562

申请日：2014-03-13

Applicant: INTEL CORPORATION ,  MORROW, Patrick ,  NELSON, Don ,  WEBB, Clair M. ,  JUN, Kimin ,  SON, Il-Seok

Inventor： NELSON, Don ,  WEBB, Clair M. ,  JUN, Kimin ,  SON, Il-Seok

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

Abstract translation: 描述了在器件结构下形成微电子互连的方法。 这些方法和结构可以包括在第一衬底中形成器件层，在第二衬底中形成至少一个布线层，然后将第一衬底与第二衬底耦合，其中第一衬底与第二衬底结合。