公开(公告)号：EP1833086A3

公开(公告)日：2008-08-13

申请号：EP07108693.8

申请日：2000-03-16

申请人： Fujitsu Ltd.

发明人： Hagiwara, Shingo ,  Suzuki, Hideaki ,  Noro, Kouichi ,  Takeshima, Tohru ,  Inami, Masaji ,  Nagai, Eiichi ,  Inoue, Amane

IPC分类号： H01L21/82 ,  H01L27/02 ,  H01L23/58 ,  H01L27/10

CPC分类号： H01L27/10 ,  H01L22/32 ,  H01L24/06 ,  H01L27/112 ,  H01L2224/05554 ,  H01L2224/4943 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/48 ,  H01L2924/00

摘要： On a semiconductor wafer, there are formed chip areas for storing memory areas, scribe areas for cutting the semiconductor wafer, pads for supplying electric signals from the outside in order to write data into the memory areas, and lead wires for electrically connecting the pads with the memory areas. The pads are formed within the scribe areas. After data has been written into the memory areas through the pads, the semiconductor wafer is cut along the scribe areas, thereby obtaining semiconductor chips. At the time of this cutting, the pads or the lead wires are cut.

摘要翻译： 在半导体晶片上，形成用于存储存储区域的芯片区域，用于切割半导体晶片的划片区域，用于从外部提供电信号的焊盘，以将数据写入存储区域，以及用于将焊盘电连接的引线与用 内存区域。 垫片形成在划线区域内。 在通过焊盘将数据写入存储区域之后，沿着划线区域切割半导体晶片，从而获得半导体芯片。 在切割时，切割焊盘或引线。

公开(公告)号：EP1906452A4

公开(公告)日：2008-07-09

申请号：EP06729669

申请日：2006-03-22

申请人： SANKEN ELECTRIC CO LTD

发明人： TORII KATSUYUKI

IPC分类号： H01L29/739 ,  H01L21/3205 ,  H01L23/498 ,  H01L23/52 ,  H01L25/04 ,  H01L25/07 ,  H01L27/00 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L25/071 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/49 ,  H01L25/18 ,  H01L25/50 ,  H01L29/7395 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A reliable semiconductor device is provided which comprises lower and upper IGBTs 1 and 2 preferably bonded to each other by solder, and a wire strongly connected to lower IGBT 1. The semiconductor device comprises a lower IGBT 1, a lower electrode layer 5 secured on lower IGBT 1, an upper electrode layer 6 secured on lower electrode layer 5, an upper IGBT 2 secured on upper electrode layer 6, and a solder layer 7 which connects upper electrode layer 6 and upper IGBT 2. Lower and upper electrode layers 5 and 6 are formed of different materials from each other, and upper electrode layer 6 has a notch 36 to partly define on an upper surface 5a of lower electrode layer 5 a bonding region 15 exposed to the outside through notch 36 so that one end of a wire 8 is connected to bonding region 15. Upper electrode layer 6 can be formed of one material superior in soldering, and also, lower electrode layer 5 can be formed of another material having a high adhesive strength to wire 8.

摘要翻译： 下部IGBT和上部IGBT通过焊料良好且牢固地结合，下部IGBT和导线牢固地连接，并且形成高度可靠的半导体器件。 该半导体器件设置有牢固地结合到下IGBT（1）的下电极层（5）; 牢固地结合到下电极层（5）的上电极层（6）; 上部IGBT（2）牢固地结合到上部电极层（6）; 和用于连接上电极层（6）和上IGBT（2）的焊料（7）。 下电极层（5）和上电极层（6）由不同的材料形成，从设置在上电极层（6）上的缺口部分（36）部分地暴露于外部的电线连接区域（15）是 布置在下电极层（5）的上平面（5a）上，并且电线（8）连接到电线连接区域（15）。 上电极层（6）由具有优异可焊性的材料形成，并且下电极层（5）由与导线（8）具有高连接强度的材料形成。

公开(公告)号：EP1909325A1

公开(公告)日：2008-04-09

申请号：EP06781411.1

申请日：2006-07-21

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： KITABATAKE, Makoto, Matsushita Electric Ind. Co.,Ltd. ,  KUSUMOTO, Osamu, Matsushita Electric Ind. Co.,Ltd. ,  UCHIDA, Masao, Matsushita Electric Ind. Co.,Ltd. ,  YAMASHITA, Kenya, Matsushita Electric Ind. Co.,Ltd.

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/12 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L29/7806 ,  H01L23/62 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/7811 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/4868 ,  H01L2224/48724 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/4878 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48744

摘要： A semiconductor element (20) of the present invention includes a plurality of field effect transistors (90) and a schottky electrode (9a), and the schottky electrode (9a) is formed along an outer periphery of a region where the plurality of field effect transistors (90) are formed.

摘要翻译： 本发明的半导体元件（20）包括多个场效应晶体管（90）和肖特基电极（9a），肖特基电极（9a）沿着多个场效应区域的外周形成 形成晶体管（90）。

公开(公告)号：EP1892754A2

公开(公告)日：2008-02-27

申请号：EP07020495.3

申请日：1998-04-28

申请人： Unitive International Limited

发明人： Rinne, Glenn, A. ,  Lizzul, Christine

IPC分类号： H01L21/60

CPC分类号： H01L24/03 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of electroplating solder bumps on an integrated circuit substrate containing a plurality of active semiconductor devices in the substrate and a plurality of contact pads electrically connected to the active semiconductor devices, comprising the steps of:
forming a plating base layer which electrically shorts the plurality of contact pads together, on the substrate; and
electroplating solder bumps on the plating base layer by drawing plating current vertically through the substrate via a first plurality of parallel electrical paths formed by the plating base layer and the plurality of active semiconductor devices.

公开(公告)号：EP1770777A2

公开(公告)日：2007-04-04

申请号：EP06027122.8

申请日：1999-07-01

申请人： HITACHI, LTD. ,  Hitachi Tohbu Semiconductor,Ltd.

发明人： Kohjiro, Iwamichi ,  Kikuchi, Sakae ,  Nunogawa, Yasuhiro ,  Kondo, Shizuo ,  Adachi, Tetsuaki ,  Kagaya, Osamu ,  Sekine, Kenji ,  Hase, Eiichi ,  Yamashita, Kiichi

IPC分类号： H01L23/66

CPC分类号： H01L24/06 ,  H01L23/04 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48799 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/19032 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F1/56 ,  H03F3/195 ,  H03F3/213 ,  H03F3/604 ,  H03F2200/12 ,  H03F2200/168 ,  H03F2200/222 ,  H03F2200/255 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/423 ,  H03F2200/451 ,  H03F2200/543 ,  H03H7/383 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/183 ,  H05K3/403 ,  H01L2924/05432 ,  H01L2924/2065 ,  H01L2224/45099 ,  H01L2924/00

摘要： In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is placed at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is. Particularly, in a high-frequency power amplifier module provided with a semiconductor chip having multistage amplifying transistors on a wiring substrate: an angle formed by a first auxiliary line connecting bonding portions to each other at the two ends of an input bonding wire connecting a bonding input electrode for a specific one of the amplifying transistors to the wiring substrate and a second auxiliary line connecting bonding portions to each other at the two ends of an output bonding wire connecting an bonding output electrode for another amplifying transistor at a stage following the specific amplifying transistor to the wiring substrate is in the range 72 degrees to 180 degrees; and a gap between bonding portions of the bonding input electrode and the bonding output electrode is at least 0.3 mm but smaller than 0.8 mm. As a result, the high-frequency characteristic of the power amplifier module can be improved and the size thereof can be reduced.

摘要翻译： 在诸如高频功率放大器模块的半导体器件中，在安装在布线基板（6000）的主表面上的半导体芯片（1000）上形成多个放大装置，并且半导体芯片的电极 通过导线与布线基板的电极电连接。 为了使高频功率放大器模块尺寸变小，将电连接到固定参考电位的线的衬底侧接合电极放置在比半导体芯片的离开半导体芯片的一侧更远的位置处， 电连接到输出线的侧面输出电极。 电连接到输入线的基板侧输入电极位于与半导体芯片的侧面相距一定距离处，等于从半导体芯片的侧面到基板侧输出电极的距离，或者距离半导体芯片 半导体芯片的侧面比基板侧接合电极为止。 具体地说，在具有在布线基板上具有多级放大晶体管（2000,3000）的半导体芯片的高频功率放大器模块中，由在输入端的两端彼此连接接合部的第一辅助线形成的角度 将用于特定一个放大晶体管的接合输入电极（2000B）连接到布线基板的接合线（9000D）和连接接合部的输出接合线（9000A）的两端彼此连接接合部的第二辅助线 另一放大晶体管的接合输出电极（3000C）在与特定放大晶体管相邻的阶段到布线基板处于72度至180度的范围内; 并且接合输入电极和接合输出电极的接合部之间的间隙为至少0.3mm但小于0.8mm。 结果，可以提高功率放大器模块的高频特性，并且可以减小其尺寸。

公开(公告)号：EP1684339A3

公开(公告)日：2007-03-14

申请号：EP06001010.5

申请日：2006-01-18

申请人： SEIKO EPSON CORPORATION

发明人： Nakayama, Hirohisa ,  Sato, Shiro ,  Shoji, Masanobu ,  Nosaka, Hitoshi

IPC分类号： H01L21/60

CPC分类号： H05K3/3489 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02166 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06131 ,  H01L2224/06155 ,  H01L2224/11 ,  H01L2224/1191 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014

摘要： A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.

公开(公告)号：EP1212797B1

公开(公告)日：2006-11-15

申请号：EP00967585.1

申请日：2000-09-15

申请人： Infineon Technologies AG

发明人： GOSSNER, Harald

IPC分类号： H01L27/02

CPC分类号： H01L27/0255 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to an ESD protective arrangement. An additional ESD diode (14) is provided between a powerbus (1) with a potential VSSP and a supply bus (8) with a potential VDDP for closing a protective path for negative charges between a substrate bus (2) with a substrate potential VSSB and the power bus (1) with the potential VSSP during an ESD stress.

公开(公告)号：EP1553640A4

公开(公告)日：2006-09-06

申请号：EP03766716

申请日：2003-08-01

申请人： NICHIA CORP

发明人： KUSUSE TAKESHI ,  SAKAMOTO TAKAHIKO

IPC分类号： H01L27/15 ,  H01L33/08 ,  H01L33/10 ,  H01L33/14 ,  H01L33/20 ,  H01L33/32 ,  H01L33/38 ,  H01L33/44 ,  H01L33/62 ,  H01L33/00

CPC分类号： H01L33/60 ,  H01L24/06 ,  H01L24/45 ,  H01L24/49 ,  H01L27/156 ,  H01L33/08 ,  H01L33/20 ,  H01L33/32 ,  H01L33/385 ,  H01L33/62 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/0106 ,  H01L2924/01063 ,  H01L2924/01065 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/0107 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/00012

摘要： A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the periphery. An n electrode is disposed on the exposed surface of the n-type semiconductor layer. This device structure can enhance the emission efficiency and the light extraction efficiency.

摘要翻译： 氮化物半导体发光器件包括在衬底上发光的层状部分。 层叠部分包括n型半导体层，有源层和p型半导体层。 层叠部的周边倾斜，并且n型半导体层的表面在周边露出。 n电极设置在n型半导体层的暴露表面上。 该器件结构可以提高发光效率和光提取效率。

公开(公告)号：EP1376694A3

公开(公告)日：2006-08-23

申请号：EP03009006.2

申请日：2003-04-17

申请人： SANYO ELECTRIC CO., LTD.

发明人： Asano, Tetsuro ,  Sakakibara, Mikito

IPC分类号： H01L23/66 ,  H01L23/485 ,  H01L23/552

CPC分类号： H01L24/05 ,  H01L23/4824 ,  H01L23/552 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L27/0605 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01037 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor switching circuit device includes a field effect transistor having a source (13), a gate electrode (17) and a drain electrode (15), a first electrode pad connected to the source electrode (13) or the drain electrode (15), and a second electrode pad connected to the source electrode (13) or the drain electrode (15) which is not connected to the first electrode pad (IN). The device also includes a third electrode pad receiving a DC voltage and applying the DC voltage to the field effect transistor, a first insulating layer (60) covering the field effect transistor, a metal layer (70) disposed above the first insulating layer (60) and connected to the third electrode pad, and a second insulating layer (80) disposed on the metal layer (70). The third electrode pad may be a control terminal pad, a ground terminal pad or a terminal pad receiving a constant DC power voltage. The metal layer (70) may be a flat sheet, a lattice or a comb-like structure.

摘要翻译： 一种半导体开关电路器件，包括具有源极（13），栅极电极（17）和漏极（15）的场效应晶体管，连接到源电极（13）或漏电极（15）的第一电极焊盘， 以及连接到未连接到第一电极焊盘（IN）的源电极（13）或漏电极（15）的第二电极焊盘。 该装置还包括：接收DC电压并将DC电压施加到场效应晶体管的第三电极焊盘;覆盖场效应晶体管的第一绝缘层（60）;设置在第一绝缘层（60）上方的金属层 ）并连接到第三电极焊盘，以及设置在金属层（70）上的第二绝缘层（80）。 第三电极焊盘可以是控制端子焊盘，接地端子焊盘或接收恒定DC电源电压的端子焊盘。 金属层（70）可以是平板状，格子状或梳状结构。

公开(公告)号：EP1686621A1

公开(公告)日：2006-08-02

申请号：EP05002108.8

申请日：2005-02-02

申请人： INTERNATIONAL RECTIFIER CORPORATION

发明人： Weidong, Zhuang

IPC分类号： H01L23/15 ,  H01L23/498

CPC分类号： H01L23/10 ,  H01L23/047 ,  H01L23/057 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A high reliability package which includes electrical terminals (12,14) formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate (10).

摘要翻译： 一种高可靠性封装，其包括由钨铜合金形成并钎焊在陶瓷基板（10）的表面上的电端子（12,14）。