公开(公告)号：EP1936677A3

公开(公告)日：2009-11-11

申请号：EP07024790.3

申请日：2007-12-20

Applicant: TDK Corporation

Inventor： Kawabata, Kenichi ,  Nagase, Kenji

IPC: H01L21/60 ,  H01L23/538

CPC classification number: H05K3/4007 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/061 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09645 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Provided is a wiring structure and the like which can completely connect a wiring layer to a body to be wired while keeping insulation between two adjacent wiring layers and realize high density packaging due to a narrowed pitch.
In a semiconductor-embedded substrate (1), a conductive pattern (13) is formed on both sides of a core substrate (11) and a semiconductor device (14) is placed in a resin layer (16) stacked over the core substrate. The resin layer has via-holes (19a,19b) so that the conductive pattern and a bump (14p) of the semiconductor device protrude from the resin layer. Inside the via-holes, the bump and conductive pattern are respectively connected to via-hole electrode portions (23a,23b) whose cross-sectional area has been increased toward the bottom of the via-hole. A void is defined between the via-hole electrode portion and upper portion of the inner wall of the via-hole.

公开(公告)号：EP1232677B1

公开(公告)日：2009-09-09

申请号：EP01951916.4

申请日：2001-07-18

Applicant: Panasonic Corporation

Inventor： MORIMOTO, Kenji ,  OCHI, Hiroshi

IPC: H05K1/11 ,  H05K3/32 ,  H05K3/06 ,  H05K1/09 ,  H01L21/48 ,  H01L21/60

CPC classification number: H01L24/16 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/45144 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/3025 ,  H05K1/092 ,  H05K1/111 ,  H05K3/02 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/098 ,  H05K2201/10674 ,  H05K2203/0514 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

Abstract: According to the present invention, when a semiconductor element (7) having protruding electrodes (5) formed thereon is connected to a circuit board (1) via conductive resin (6), stable connection is made even when an electrode pitch is small on the semiconductor element (7). On semiconductor element package regions on the circuit board (1), a paste electrode material (2) containing photopolymerizable materials is printed to form a film having a prescribed thickness, and this electrode material film (2) is baked after exposure and development thereof so as to obtain circuit electrodes (4) having edges warped in a direction of going apart from the circuit board (1) surface. Then, the protruding electrodes (5) and the concave surfaces of the circuit electrodes (4) are brought in abutment with each other and connected via the conductive resin (6) which surrounds the abutments between the respective electrodes and is held on the concave surfaces of the circuit electrodes (4). With this arrangement, the concave surfaces of the circuit electrodes (4) act as saucers and prevent the conductive resin (6) from being squeezed out, thereby eliminating possible occurrence of short circuits.

公开(公告)号：EP2040289A2

公开(公告)日：2009-03-25

申请号：EP08250419.2

申请日：2008-02-05

Applicant: Phoenix Precision Technology Corporation

Inventor： Hsu, Shih-Ping

IPC: H01L21/60 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/498 ,  H01L23/49822 ,  H01L24/14 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/1403 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H05K3/062 ,  H05K3/108 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0574 ,  Y10T29/49165

Abstract: The present invention relates to a packaging substrate and a method for manufacturing the same. The packaging substrate comprises: a substrate body (30), wherein a surface thereof has a circuit layer comprising a plurality of circuits (33) and a plurality of conductive pads (34), and the conductive pads are higher than the circuits; and an insulating protection layer (37) disposed on the surface of the substrate body, wherein the insulating protection layer has a plurality of openings (371) exposing the conductive pads, and the size of the openings is larger than or equal to that of the conductive pads. Accordingly, the packaging substrate structure of the present invention can be employed in a flip-chip packaging structure of fine-pitch.

Abstract translation: 封装基板及其制造方法技术领域本发明涉及一种封装基板及其制造方法。 所述封装基板包括：基板本体，所述基板本体的表面具有电路层，所述电路层包括多个电路以及多个导电焊盘，所述导电焊盘高于所述电路; 以及绝缘保护层（37），设置在所述衬底本体的表面上，其中，所述绝缘保护层具有暴露所述导电焊盘的多个开口（371），并且所述开口的尺寸大于或等于 导电垫。 因此，本发明的封装基板结构可应用于微间距的倒装芯片封装结构。

公开(公告)号：EP2039517A1

公开(公告)日：2009-03-25

申请号：EP08022399.3

申请日：2006-03-24

Applicant: Brother Kogyo Kabushiki Kaisha

Inventor： Banno, Takaaki ,  Shinkai, Yuji

IPC: B41J2/16 ,  B41J2/14

CPC classification number: H05K3/363 ,  B41J2/14209 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2/1643 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14459 ,  B41J2002/14491 ,  B41J2202/20 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/10977

Abstract: A method for manufacturing bonded substrates includes: forming the first terminals on the first substrate, the first terminals each having a metal core projecting from a surface of the first substrate, each metal core coated with a solder layer lower in a melting point than the metal core; forming the conductive second terminals on the second substrate; and electrically bonding the first terminals to the second terminals by heating the first and second substrates while applying pressure to the first substrate and the second substrate. In the forming of the first terminals, a ratio of a height of the metal core from the surface of the first substrate in a thickness direction of the first substrate to a thickness of the solder layer in the thickness direction of the first substrate is in a range of from 1:1 to 2:1.

Abstract translation: 一种用于制造键合衬底的方法，包括：在第一衬底上形成第一端子，第一端子均具有从第一衬底的表面突出的金属芯，每个金属芯涂覆有熔点低于金属的焊料层 核心; 在第二基板上形成导电的第二端子; 以及通过在对所述第一基板和所述第二基板施加压力的同时加热所述第一和第二基板来将所述第一端子电连接到所述第二端子。 在形成所述第一端子时，所述金属芯相对于所述第一基板的厚度方向的所述第一基板的表面的高度相对于所述第一基板的厚度方向的厚度成为 范围从1：1到2：1。

公开(公告)号：EP1926136A3

公开(公告)日：2008-10-29

申请号：EP07022679.0

申请日：2007-11-22

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Murayama, Kei ,  Taguchi, Yuichi ,  Shiraishi, Akinori ,  Sunohara, Masahiro ,  Higashi, Mitsutoshi

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/14 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L23/147 ,  H01L21/4846 ,  H01L23/02 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/162 ,  H01L25/167 ,  H01L25/50 ,  H01L33/486 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1461 ,  H05K3/4015 ,  H05K3/4614 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/049 ,  H05K2203/0733 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of manufacturing an electronic component includes the steps of: a) forming a plurality of wiring boards (100, 200; 300) that include first through holes (101A, 20 1 A; 301 A) penetrating through a semiconductor substrate and conductive material (104, 204; 305) buried in the first through holes; b) providing conductive projections (107; 310) on the conductive material of any of the plurality of wiring boards; and c) bonding the plurality of wiring boards to each other and electrically connecting the conductive material of the respective wiring boards by the projections.

公开(公告)号：EP1926136A2

公开(公告)日：2008-05-28

申请号：EP07022679.0

申请日：2007-11-22

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Murayama, Kei ,  Taguchi, Yuichi ,  Shiraishi, Akinori ,  Sunohara, Masahiro ,  Higashi, Mitsutoshi

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/14 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L23/147 ,  H01L21/4846 ,  H01L23/02 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/162 ,  H01L25/167 ,  H01L25/50 ,  H01L33/486 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1461 ,  H05K3/4015 ,  H05K3/4614 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/049 ,  H05K2203/0733 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of manufacturing an electronic component includes the steps of: a) forming a plurality of wiring boards (100, 200; 300) that include first through holes (101A, 20 1 A; 301 A) penetrating through a semiconductor substrate and conductive material (104, 204; 305) buried in the first through holes; b) providing conductive projections (107; 310) on the conductive material of any of the plurality of wiring boards; and c) bonding the plurality of wiring boards to each other and electrically connecting the conductive material of the respective wiring boards by the projections.

Abstract translation: 一种制造电子元件的方法，包括以下步骤：a）形成多个布线板（100,200,300），所述多个布线板包括贯穿半导体衬底的第一通孔（101A，201A; 301A）和导电材料 （104,204; 305），埋在所述第一通孔中; b）在所述多个线路板中的任何一个的导电材料上提供导电凸起（107; 310）; 以及c）将多个布线板相互接合并通过突起电连接各个布线板的导电材料。

公开(公告)号：EP1863327A1

公开(公告)日：2007-12-05

申请号：EP05766427.8

申请日：2005-07-21

Applicant: Cluster Technology Co., Ltd

Inventor： FUJIMOTO, Takayoshi, Cluster Technology Co., Ltd. ,  KITAOKA, Kenji, Cluster Technology Co., Ltd.

IPC: H05K3/10 ,  H05K1/14 ,  H05K3/36

CPC classification number: H05K3/4007 ,  H05K1/0284 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/182 ,  H05K3/246 ,  H05K3/3436 ,  H05K3/4614 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09472 ,  H05K2203/0709 ,  H05K2203/1173 ,  H05K2203/1189 ,  H05K2203/1476 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring circuit board and a method of producing the same are provided in which a desired pattern of wiring is provided at higher density while permitting no overflow from the grooves of an electroless plating catalyst containing solution and an electric conductor forming liquid such as silver ink.
The pattern of electric conductor is deposited by applying the electric conductor forming liquid into the grooves provided in a substrate and distributing the same along the grooves with the action of capillarity. The method starts with patterning the grooves in the surface of the substrate (S1), applying the electric conductor forming liquid into the grooves (S2), and coating the surface of the substrate with a layer of repellent liquid which is lower in the affinity with the electric conductor forming liquid (S3). This is followed by cleaning at least the grooves (S4) and then filling the grooves with the electric conductor forming liquid once again (S5). The electric conductor forming liquid applied into the grooves is then distributed throughout the grooves by the action of capillarity. When silver ink is used, the pattern of electric conductor is produced by repeating an action of applying and drying a number of times. Alternatively, the patter of electric conductor can be produced by an electroless plating technique or a combination of an electroless plating technique and an electro-plating technique for separating an electrical conductive material form the electric conductor forming liquid.

Abstract translation: 提供了一种布线电路板及其制造方法，其中以更高的密度提供所需的布线图形，同时不会从含化学镀电镀催化剂溶液的槽和诸如银墨的电导体形成液体的槽中溢出。 通过将导电剂形成液体施加到设置在基板中的凹槽中并通过毛细管作用沿着凹槽分布而将电导体的图案沉积。 该方法开始于图案化基板表面上的凹槽（S1），将导电剂形成液体施加到凹槽（S2）中，并且用一层与亲水性相差较小的驱避液体涂覆基板的表面， 导电体形成液体（S3）。 然后，至少清洗槽（S4），然后再次用导电体形成液填充槽（S5）。 然后通过毛细作用的作用将施加到槽中的电导体成形液分布在整个凹槽中。 当使用银墨时，通过重复施加和干燥多次的动作来产生电导体的图案。 或者，电导体的图案可以通过化学镀技术或化学镀技术和用于从形成电导体的液体分离导电材料的电镀技术的组合来制造。

公开(公告)号：EP1845760A1

公开(公告)日：2007-10-17

申请号：EP06712385.1

申请日：2006-01-26

Applicant: Sony Chemical & Information Device Corporation

Inventor： SUZUKI, Kazuaki c/o Sony Chemical & Info Device Corp. ,  TANIGUCHI, Masaki c/o Sony Chemical & Info Device Corp

IPC: H05K1/14 ,  H01R11/01

CPC classification number: H05K3/368 ,  H01R12/52 ,  H01R13/2414 ,  H05K1/186 ,  H05K3/325 ,  H05K3/4611 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/10636 ,  H05K2201/10977 ,  Y02P70/611

Abstract: A connecting part for ensuring connection is provided. In this connecting part 1, first connecting terminals 13a are arranged on one face of a supporting member 11 made of an elastic body, and second connecting terminals 13b are arranged on the back face of the supporting member 11. The connecting terminals 13a, 13b are interconnected by conductive films 12a, 12b, and 12c which are formed on the face of the supporting member 11. Connecting parts 1 are arranged between circuit boards on which electronic parts are mounted, and the circuit boards are mutually fixed in the state in which the connecting parts 1 are compressed. The first and second connecting terminals 13a, 13b are pushed against lands on the circuit boards by restoring force of the connecting parts 1, and then the circuit boards are electrically interconnected.

Abstract translation: 提供用于确保连接的连接部件。 在该连接部1中，第一连接端子13a配置在由弹性体构成的支撑部件11的一个面上，第二连接端子13b配置在支撑部件11的背面。连接端子13a，13b为 通过形成在支撑构件11的表面上的导电膜12a，12b和12c相互连接。连接部分1布置在其上安装电子部件的电路板之间，并且电路板相互固定，其中 连接部件1被压缩。 第一和第二连接端子13a，13b通过连接部件1的恢复力而被推靠在电路板上的平台上，然后电路板电互连。

公开(公告)号：EP1450405A3

公开(公告)日：2007-08-29

申请号：EP04002985.2

申请日：2004-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwang, Seong-Yong ,  Kang, Sung-Chul ,  Oh, Weon-Sik ,  Jeong, Cheol-Yong ,  Lee, Jin-Suk ,  Yoon, Ju-Young ,  Cho, Won-gu

IPC: G02F1/13 ,  H01L21/60 ,  H01L23/538 ,  H01L23/498

CPC classification number: G02F1/13452 ,  G02F2001/13456 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81801 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/323 ,  H05K2201/0367 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a drive IC and a display device having the same, the drive IC includes a plurality of bumps disposed on a lower surface of the drive IC and aligned in a plurality of rows along an edge of the drive IC. The bumps aligned in different rows from each other are juxtaposed in a direction perpendicular to a direction in which the bumps are aligned. Accordingly, when the drive IC is mounted on a display panel using an anisotropic conductive film, the anisotropic conductive film may be smoothly flowed through a space defined by the bumps of the drive IC, thereby improving electric properties of the drive IC and display device.

公开(公告)号：EP1193755A4

公开(公告)日：2007-07-11

申请号：EP00937200

申请日：2000-06-09

Applicant: TOYO KOHAN CO LTD

Inventor： SAIJO KINJI ,  YOSHIDA KAZUO ,  OKAMOTO HIROAKI ,  OHSAWA SHINJI

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/06 ,  H05K3/28 ,  H05K3/40 ,  H01L23/12 ,  B23K20/00

CPC classification number: H01L23/3114 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49861 ,  H01L2224/16 ,  H01L2924/07811 ,  H05K3/062 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2203/0384 ,  H05K2203/1572 ,  Y10T29/30 ,  Y10T29/301 ,  Y10T29/302 ,  Y10T29/49002 ,  Y10T428/1291 ,  H01L2924/00

Abstract: A clad plate for forming an interposer for a semiconductor device which can be manufactured at low cost and has good characteristics, an interposer for a semiconductor device, and a method of manufacturing them. Copper foil materials (19, 24, 33) forming conductive layers (10, 17, 18) and nickel plating (20, 21) forming etching stopper layers (11, 12) are formed and pressed to form a clad plate (34) for forming an interposer for a semiconductor device. Thus, a clad plate (34) for forming an interposer for a semiconductor device is manufactured. The clad plate (34) is selectively etched to form a columnar conductor (17), and an insulating layer (13) is formed on the copper foil material forming a wiring layer (10). A bump (18) for connection of a semiconductor chip and the wiring layer (10) are formed on the opposite side to the side on which the columnar conductor (17) is formed. Thus, an interposer for a semiconductor device is manufactured.