公开(公告)号：EP1659841A3

公开(公告)日：2009-02-25

申请号：EP06003039.2

申请日：1999-07-07

Applicant: IBIDEN CO., LTD.

Inventor： Tsukada, Kiyotaka ,  Takada, Masaru ,  Chihara, Kenji

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0265 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0554 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A printed circuit board and a method for manufacturing the same that facilitates the formation of an upper surface pattern and prevents a lower surface metal foil from being damaged when forming a blind via hole with a laser is provided. A lower surface and an upper surface of an insulative substrate (5) are respectively coated with a lower surface metal foil (220) and an upper surface metal foil (210), the thickness of which is less than that of the lower surface metal foil (220). Next, an opening (213) is formed in the upper surface metal foil at a location corresponding to a blind via hole formation portion (35) of the insulative substrate. A blind via hole (3), the bottom of which is the lower surface metal foil, is formed by emitting a laser (8) against the blind via hole formation portion (35) through the opening (213). Then, a metal plating film (23) is applied to the wall of the blind via hole (3), and an upper surface pattern (21) and a lower surface pattern (22) are formed through etching.

公开(公告)号：EP2007179A2

公开(公告)日：2008-12-24

申请号：EP07737869.3

申请日：2007-03-06

Applicant: Nippon Mektron, Limited

Inventor： MATSUDA, Fumihiko

IPC: H05K3/46

CPC classification number: H05K3/4626 ,  H05K1/118 ,  H05K3/002 ,  H05K3/281 ,  H05K3/386 ,  H05K3/4691 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2203/0554

Abstract: To provide a thin multilayer flexible circuit board having cable portions drawn out of a plurality of outer layers, and a method for manufacturing the same. A multilayer flexible circuit board including a parts mounting portion having an inner-layer board 107 and outer-layer boards 106, and cable portions drawn out of at least one of the inner-layer board and outer-layer boards, wherein each of the inner-layer board and the outer-layer boards has circuits facing one another, characterized by each of the circuits facing one another is covered with a cover 5 formed of a cover film in common with the cable portion: and a method for manufacturing the same.

Abstract translation: 提供具有从多个外层引出的电缆部分的薄多层柔性电路板及其制造方法。 一种多层柔性电路板，包括具有内层板107和外层板106的部分安装部分和从内层板和外层板中的至少一个引出的电缆部分，其中内部 层叠板和外层板具有彼此面对的电路，其特征在于，彼此面对的每个电路被覆盖有由与电缆部分共同的覆盖膜形成的盖5及其制造方法。

公开(公告)号：EP1699275A3

公开(公告)日：2008-10-29

申请号：EP06004062.3

申请日：2006-02-28

Applicant: Samsung Electro-Mechanics Co., Ltd

Inventor： Ahn, Jin Yong ,  Hwang, Cheol Seong ,  Kim, Sung Kun ,  Ryu, Chang Sup ,  Cho, Suk Hyeon ,  Jeon, Ho Sik

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L2924/0002 ,  H05K1/095 ,  H05K3/108 ,  H05K3/244 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09881 ,  Y10S438/957 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Disclosed is a printed circuit board (101) having embedded capacitors therein, comprising: a double-sided copper-clad laminate including first circuit layers formed in the outer layers (102) thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers (105) formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers (106) formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates (108;109) formed on the second circuit layers; blind via-holes (111) and through-holes (110) formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes (111) and the through-holes (110). The manufacturing method of the printed circuit board is also disclosed.

公开(公告)号：EP1953870A1

公开(公告)日：2008-08-06

申请号：EP06823175.2

申请日：2006-11-08

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： OKUDA, Yasuhiro ,  HOSOE, Akihisa ,  FUJITA, Taro

IPC: H01R11/01 ,  H01B5/16 ,  H01B13/00 ,  H01R43/00

CPC classification number: H01R13/03 ,  H01R4/04 ,  H01R11/01 ,  H01R43/0235 ,  H01R43/0249 ,  H01R43/0256 ,  H05K3/0035 ,  H05K3/326 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/0156 ,  Y10T29/49204

Abstract: Provided is an anisotropic conductive sheet (8) having heat resistance and cold resistance and suitable for connection of electrodes. The anisotropic conductive sheet of the present invention has conductivity in the thickness direction, wherein the base film (1), which is a film made of synthetic resin having an electrical insulation property, has a plurality of holes (3) formed in the thickness direction, and the holes (3) are open to one main surface of the base film and closed to the other main surface, wherein a metal is adhered to the closed parts (2a) and the inner walls (2b) of the holes (3) so that by contacting electrodes (7) with the closed parts (2a) respectively from the outside, the electrodes (7) can electrically be connected through the adhered metal to the main surface where the holes (3) are open.

Abstract translation: 提供具有耐热性和耐寒性并适合于电极连接的各向异性导电片（8）。 本发明的各向异性导电片在厚度方向上具有导电性，其中作为由具有电绝缘性的合成树脂制成的膜的基膜（1）具有沿厚度方向形成的多个孔（3） ，并且所述孔（3）对所述基膜的一个主表面开放并且与另一个主表面闭合，其中金属粘附到所述封闭部分（2a）和所述孔（3）的内壁（2b） 使得通过分别从外部将电极（7）与闭合部分（2a）接触，电极（7）可以通过粘附的金属电连接到孔（3）打开的主表面。

公开(公告)号：EP1019986B1

公开(公告)日：2008-06-18

申请号：EP98952161.2

申请日：1998-10-07

Applicant: Dimensional Circuits Corp.

Inventor： GREGOIRE, George, D.

IPC: H05K3/46 ,  H05K3/00 ,  H01R12/32

CPC classification number: H05K3/005 ,  H05K1/095 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/061 ,  H05K3/107 ,  H05K3/1241 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09863 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/041 ,  H05K2203/0746 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A wiring board construction (10) includes at least one microvia (12) disposed in a base substrate (14) and includes a deep imprinted cup shaped in the top surface thereof (24). A conductor material is disposed within the recess (26), and has a portion disposed at the bottom thereof. A conductor disposed at a bottom surface of the substrate opposite to the conductor material bottom portion (31) helps to complete an electrically conductive path through the substrate.

公开(公告)号：EP1923488A2

公开(公告)日：2008-05-21

申请号：EP08152453.0

申请日：1999-09-14

Applicant: Ibiden Co., Ltd.

Inventor： En, Honchin ,  Nakai, Tohru ,  Oki, Takeo ,  Hirose, Naohiro ,  Noda, Kouta

IPC: C25D5/18

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A process for manufacturing a multilayer printed circuit board comprises a step for providing openings in an interlayer insulating layer (4002), and a step for filling up the openings with a plating metal to construct via holes (4007) and, at the same time, build up an upper-layer conductor layer (4005). The electroplating is performed using an aqueous solution containing a metal ion and 0.1 to 1.5 mmol/L of at least one additive selected from the group consisting of thioureas, cyanides and polyalkylene oxides as a plating solution.

Abstract translation: 一种制造多层印刷电路板的方法包括在层间绝缘层（4002）中提供开口的步骤，以及用电镀金属填充开口以构造通孔（4007）的步骤，同时， 建立上层导体层（4005）。 使用含有金属离子的水溶液和0.1〜1.5mmol / L的选自硫脲，氰化物和聚环氧烷作为电镀液的至少一种添加剂进行电镀。

公开(公告)号：EP1259102B1

公开(公告)日：2008-01-09

申请号：EP01111661.3

申请日：2001-05-14

Applicant: OKI PRINTED CIRCUITS CO., LTD.

Inventor： Iinaga, Hiroshi

IPC: H05K3/46

CPC classification number: H05K1/115 ,  H05K3/4623 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09854

公开(公告)号：EP1827068A3

公开(公告)日：2007-10-03

申请号：EP07075317.3

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki c/o Ibiden Co., Ltd. ,  Minoura, Hisashi c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro c/o Ibiden Co., Ltd.

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A printed wiring board (802) comprising an insulating substrate (806), a conductor pattern formed on a surface of the insulating substrate (806), a solder filling hole (801) passing through the insulating substrate (806) and arriving at an upper surface of the conductor pattern (851) and a solder (807) filled in the solder filling hole (801), characterized in that the insulating substrate (806) includes fibers (861) therein, and end portions (863) of the fibers (861) protrude from a wall face (810) of the solder filling hole (801) and encroach into the solder (807).

Abstract translation: 一种印刷线路板（802），包括：绝缘基板（806）;在绝缘基板（806）的表面上形成的导体图案;贯通绝缘基板（806）并到达上部 （801）和填充在所述焊料填充孔（801）中的焊料（807），其特征在于，所述绝缘基底（806）中包括纤维（861），所述纤维（861）的端部（863） 861）从焊料填充孔（801）的壁面（810）突出并侵入到焊料（807）中。

公开(公告)号：EP1102525B1

公开(公告)日：2007-09-19

申请号：EP99929729.4

申请日：1999-07-07

Applicant: IBIDEN CO., LTD.

Inventor： TSUKADA, Kiyotaka, Ibiden Co., Ltd. ,  TAKADA, Masaru, Ibiden Co., Ltd. ,  CHIHARA, Kenji, Ibiden Co., Ltd.

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0265 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0554 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A printed wiring board and method for producing the same, in which an upper-surface pattern is readily formed, and a lower-surface metal foil is hardly damaged when a blind via hole is made by a laser beam. A lower-surface metal foil (220) is provided over the lower surface of an insulating sheet (5), and an upper-surface metal foil (210) thinner than the lower-surface metal foil (220) is provided over its upper surface. An open hole (213) is made in the upper-surface metal foil in a position corresponding to the area (35) where a blind via hole is formed. A laser beam (8) is projected onto the area (35) through the open hole (213) to make a blind via hole (3) the bottom of which is the lower-surface metal foil. A metal plating film (23) is formed on the inner wall of the blind via hole (3). Upper- and lower-surface patterns (21, 22) are formed by etching.

公开(公告)号：EP0883173B1

公开(公告)日：2007-09-12

申请号：EP96930376.7

申请日：1996-09-12

Applicant: IBIDEN CO., LTD.

Inventor： ASAI, Motoo ,  KAWAMURA, Yoichiro ,  MORI, Yoji

IPC: H01L23/12 ,  H05K1/03 ,  H05K1/11

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/523 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/114 ,  H05K3/184 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0212 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: A circuit board for mounting electronic parts, which includes first connecting terminal groups (12A and 12B) composed of a plurality of connecting terminals densely formed on the front surface (S1) of a base substrate (2) having through holes (6) and a second connecting terminal group (13) composed of a plurality of connecting terminals formed in at least outer peripheral section on the rear surface (S2) of the substrate (2). The first groups (12A and 12B) are connected to the second group (13) through the holes (6). On the front surface of the substrate (2), build-up multilayered wiring layers (B1 and B2) having via holes (11) are formed and the first groups (12A and 12B) are connected to the second group (13) through the wiring layers (B1 and B2) and through holes (6). In another example, each signal line (52) on the surfaces of the wiring layers (B1 and B2) is composed of a plurality of wiring patterns (58 and 59) having different line widths and a tapered pattern (60) which connects the wiring patterns (58 and 59) to each other and the width of which continuously varies. The line width of the signal line (52) in an area where the wiring density is relatively high is made narrower than that in another area where the wiring density is relatively low.