公开(公告)号：EP3378288A1

公开(公告)日：2018-09-26

申请号：EP16785648.3

申请日：2016-10-11

Applicant: Northrop Grumman Systems Corporation

Inventor： CHRISTIANSEN, Martin Brokner ,  CHOROSINSKI, Leonard George ,  HEFFNER, H. Craig ,  WAKAMIYA, Stanley Katsuyoshi ,  KIRKWOOD, Keith R.

IPC: H05K1/02 ,  H01L39/22 ,  H05K1/03

CPC classification number: H05K1/181 ,  H05K1/0203 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/303 ,  H05K3/46 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/09063 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09763

Abstract: A circuit card assembly includes a substrate having longitudinally spaced first and second substrate end edges and transversely spaced top and bottom substrate surfaces. The top and/or bottom substrate surface has first, second, and third substrate regions. The first substrate region is directly laterally adjacent the first substrate side edge. The third substrate region is directly laterally adjacent the second substrate side edge. The second substrate region is located between the first and third substrate regions. At least one circuit trace is located on the selected substrate surface. The portion of the circuit trace in the first substrate region is made of only a first material. The portion of the circuit trace in the third substrate region is made of only a second material. The portion of the circuit trace in the second substrate region is made of both the first and second materials.

公开(公告)号：EP3325264A1

公开(公告)日：2018-05-30

申请号：EP16741600.7

申请日：2016-07-18

Applicant: Rogers Germany GmbH

Inventor： MEYER, Andreas ,  SCHMIDT, Karsten

IPC: B32B5/12 ,  B32B5/20 ,  B32B7/12 ,  B32B9/00 ,  B32B9/04 ,  B32B9/06 ,  B32B29/08

CPC classification number: B32B9/005 ,  B32B5/12 ,  B32B5/20 ,  B32B7/12 ,  B32B9/041 ,  B32B9/06 ,  B32B15/043 ,  B32B15/12 ,  B32B15/20 ,  B32B29/002 ,  B32B29/08 ,  B32B2255/06 ,  B32B2255/205 ,  B32B2255/26 ,  B32B2255/28 ,  B32B2264/107 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2307/54 ,  B32B2457/08 ,  B32B2605/00 ,  C25D11/005 ,  C25D11/04 ,  C25D11/08 ,  C25D17/12 ,  H01L23/3735 ,  H05K1/0201 ,  H05K1/0313 ,  H05K1/053 ,  H05K3/4688 ,  H05K2201/0116 ,  H05K2201/0338 ,  H05K2203/0315 ,  H05K2203/11 ,  H05K2203/1126

Abstract: The invention relates to a substrate (1, 10) for electrical circuits, comprising at least one metal layer (2, 3, 14) and a paper ceramic layer (11), which is joined face to face with the at least one metal layer (2, 3, 14) and has a top side and bottom side (11a, 11b), wherein the paper ceramic layer (11) has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer (2, 3, 14) is connected to the paper ceramic layer (11) by means of at least one glue layer (6, 6a, 6b), which is produced by applying at least one glue (6a', 6a'', 6b', 6b'') to the metal layer (2, 3, 14) and/or to the paper ceramic layer (11), wherein the cavities in the form of pores in the paper ceramic layer (11) are filled at least at the surface by means of the applied glue (6a', 6a'', 6b', 6b'').

公开(公告)号：EP2457413B1

公开(公告)日：2018-03-28

申请号：EP10737706.1

申请日：2010-07-20

Applicant: PPG Industries Ohio, Inc.

Inventor： SHORT, John, R.

IPC: H05B3/84

CPC classification number: H05K1/0274 ,  H05B3/84 ,  H05B2203/016 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0326 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/10272

Abstract: A bus bar system includes a non-conductive substrate having a major surface. At least one conductive bus bar is formed over at least a portion of the major surface. A conductive coating is formed over at least a portion of the bus bar and the major surface. An electrically conductive adhesive, such as an isotropically conductive tape or film, is applied over at least a portion of the film/bus bar junction. The system can optionally include a conductive metallic foil adhered to the isotropically conductive adhesive.

公开(公告)号：EP3277062A1

公开(公告)日：2018-01-31

申请号：EP17177352.6

申请日：2017-06-22

Applicant: Fujitsu Limited

Inventor： Matsumura, Takayoshi ,  Baba, Shunji ,  Kanda, Takashi ,  Ozaki, Noritsugu ,  Kira, Hidehiko

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/24

CPC classification number: H05K1/0283 ,  H05K1/0271 ,  H05K1/092 ,  H05K1/181 ,  H05K1/189 ,  H05K3/245 ,  H05K2201/0314 ,  H05K2201/0338 ,  H05K2201/09045 ,  H05K2201/09281 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10015 ,  H05K2201/10098 ,  H05K2201/10522

Abstract: A wiring board 1 includes a base 10 having extensibility and a wiring 40 formed on the base. The wiring includes a wiring portion 20 and a conductor portion 30. The wiring portion is formed on the base and extends in a first direction P crossing (for example, perpendicular to) a longitudinal direction X of the base. The conductor portion is formed on the wiring portion and extends in the first direction. Even when the wiring board is extended along a main extension axis S in parallel with the longitudinal direction of the base, change of the resistance of the wiring is prevented. Thus, the wiring board represents stable characteristics.

Abstract translation: 布线板1包括具有延伸性的基座10和形成在基座上的布线40。 布线包括布线部分20和导体部分30.布线部分形成在基底上并且沿着与基底的纵向方向X交叉（例如，垂直于）的第一方向P延伸。 导体部分形成在布线部分上并沿第一方向延伸。 即使布线基板沿着主延伸轴S与基座的长度方向平行地延伸，也能够防止布线的电阻变化。 因此，线路板表现出稳定的特性。

公开(公告)号：EP3167992A1

公开(公告)日：2017-05-17

申请号：EP16187779.0

申请日：2016-09-08

Applicant: NEC Space Technologies, Ltd.

Inventor： OGAWA, Bunsuke

IPC: B23K1/00 ,  B23K35/26 ,  B23K20/02 ,  B23K101/38

CPC classification number: H05K3/3457 ,  B23K1/0016 ,  B23K20/026 ,  B23K35/26 ,  B23K35/268 ,  B23K2201/38 ,  H05K1/09 ,  H05K1/181 ,  H05K3/3478 ,  H05K3/3494 ,  H05K2201/0338

Abstract: [Problem]
Even if heat cycles are applied, degradation of joint strength is restrained.
[Solution to problem]
Lead solder joint structure, in which a first member (10) is joined to a second member (11) using lead solder, the structure comprising: a first solder layer (21) that includes the first member as a core; a second solder layer (22) that exists between the first solder layer and the second member and joins the first solder layer and the second member together; and a third solder layer (24) that exists between the second solder layer and the second member.

Abstract translation: [问题]即使施加热循环，也会限制接合强度的降低。 问题的解决方案使用铅焊料将第一构件（10）接合到第二构件（11）的铅焊接结构包括：包括第一构件作为芯的第一焊料层（21） ; 存在于所述第一焊料层和所述第二构件之间并且将所述第一焊料层和所述第二构件接合在一起的第二焊料层; 以及存在于第二焊料层和第二构件之间的第三焊料层（24）。

公开(公告)号：EP2991105A4

公开(公告)日：2016-12-07

申请号：EP14787718

申请日：2014-04-28

Applicant: KYOCERA CORP

Inventor： NIINO NORITAKA

IPC: H01L23/14 ,  B23K35/30 ,  B32B15/01 ,  C04B37/02 ,  H01L23/13 ,  H01L23/15 ,  H01L23/373 ,  H05K1/03 ,  H05K1/09 ,  H05K3/38

CPC classification number: B32B15/018 ,  B23K35/3006 ,  B32B15/01 ,  B32B15/04 ,  B32B18/00 ,  C04B37/026 ,  C04B2237/122 ,  C04B2237/123 ,  C04B2237/124 ,  C04B2237/125 ,  C04B2237/126 ,  C04B2237/127 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/365 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/407 ,  C04B2237/60 ,  C04B2237/706 ,  C04B2237/708 ,  C04B2237/72 ,  H01L23/13 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/388 ,  H05K2201/0338 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Problem: To provide a metal plate, a composite laminate and the like, each of which has excellent long-term reliability. Resolution means: A composite laminate (12) includes a first metal layer (1), a second metal layer (2), a third metal layer (3), and a fourth layer (4). The first metal layer (1) contains copper. The second metal layer (2) is arranged on the lower surface of the first metal layer (1). The third metal layer (3) is arranged on the lower surface of the second metal layer (2), and contains silver, at least one metal selected from a first group made up of Sn, Al, and Ga, and at least one metal selected from a second group made up of In and Sb. The fourth layer (4) is arranged on the lower surface of the third metal layer (3). The third metal layer (3) has a metal portion (2A) that partially penetrates the second metal layer (2) from the third metal layer (3).

公开(公告)号：EP2940528B1

公开(公告)日：2016-11-16

申请号：EP15165648.5

申请日：2015-04-29

Applicant: Wistron NeWeb Corp.

Inventor： Radi, Babak ,  Chen, Shih-Hong ,  Kuo, Yu-Fu ,  Chen, Chun-Lin ,  Chen, Jing-Wen

IPC: G03F7/20 ,  H01L23/06 ,  B32B15/04 ,  B32B15/08 ,  B32B15/20 ,  B32B3/02 ,  B32B3/30 ,  C23C18/16 ,  C23C18/18 ,  H01Q1/22

CPC classification number: C23C18/1605 ,  B32B3/02 ,  B32B3/30 ,  B32B15/043 ,  B32B15/08 ,  B32B15/20 ,  B32B2255/06 ,  B32B2255/205 ,  B32B2255/24 ,  B32B2457/00 ,  C23C18/182 ,  G03F7/202 ,  H01L23/06 ,  H01L2924/0002 ,  H05K1/09 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/243 ,  H05K2201/0338 ,  H05K2203/072 ,  Y10T428/12361 ,  Y10T428/24331 ,  H01L2924/00

公开(公告)号：EP2820596A4

公开(公告)日：2016-01-20

申请号：EP13764036

申请日：2013-03-20

Applicant: LG INNOTEK CO LTD

Inventor： LIM SEOL HEE

IPC: G06K19/077 ,  C25D3/14 ,  C25D3/16 ,  C25D5/02 ,  C25D5/12 ,  H05K1/18

CPC classification number: H05K1/05 ,  C25D3/14 ,  C25D3/16 ,  C25D5/022 ,  C25D5/12 ,  H01L2224/45144 ,  H01L2224/48091 ,  H05K1/11 ,  H05K1/117 ,  H05K1/181 ,  H05K3/244 ,  H05K2201/0104 ,  H05K2201/032 ,  H05K2201/0338 ,  H05K2201/10159 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A printed circuit board for a memory card includes an insulating layer; a mounting part on a first surface of the insulating layer, the mounting part being electrically connected to a memory device; and a terminal part on a second surface of the insulating layer, the terminal part being electrically connected to an external electronic appliance, wherein a same metal layer having a same property is formed on exposed surfaces of the mounting part and the terminal part.

公开(公告)号：EP2940528A1

公开(公告)日：2015-11-04

申请号：EP15165648.5

申请日：2015-04-29

Applicant: Wistron NeWeb Corporation

Inventor： Radi, Babak ,  Chen, Shih-Hong ,  Kuo, Yu-Fu ,  Chen, Chun-Lin ,  Chen, Jing-Wen

IPC: G03F7/20 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/52 ,  H01L21/48

CPC classification number: C23C18/1605 ,  B32B3/02 ,  B32B3/30 ,  B32B15/043 ,  B32B15/08 ,  B32B15/20 ,  B32B2255/06 ,  B32B2255/205 ,  B32B2255/24 ,  B32B2457/00 ,  C23C18/182 ,  G03F7/202 ,  H01L23/06 ,  H01L2924/0002 ,  H05K1/09 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/243 ,  H05K2201/0338 ,  H05K2203/072 ,  Y10T428/12361 ,  Y10T428/24331 ,  H01L2924/00

Abstract: The present disclosure is directed to a method of fabricating a substrate structure and a substrate structure fabricated by the same method. The method would include forming a first metal layer directly on a base, forming a second metal layer directly on the first metal layer, forming a first protective layer by using a compound comprising a thiol group directly on the second metal layer, patterning the first protective layer to form at least one opening exposing the second metal layer, and forming a third metal layer within the at least one opening of the first protective layer and directly on the second metal layer. The substrate structure would include a base, a first metal layer, a second metal layer, a first protective layer, at least one opening, and a third metal layer.

Abstract translation: 本发明涉及一种制造结构衬底的方法和底物由相同的方法制造的结构。 该方法将包括在基体上形成第一金属层直接地，所述第一金属层上直接形成的第二金属层，通过使用化合物的第二金属层上直接包含硫醇基团形成的第一保护层，图案化所述第一保护 层，以形成至少一个开口暴露所述第二金属层，并且形成所述第一保护层的至少一个开口，并且直接在所述第二金属层中的第三金属层。 基底结构将包括一底座，一第一金属层，第二金属层，第一保护层，至少一个开口，和第三金属层。

公开(公告)号：EP2780955A4

公开(公告)日：2015-07-15

申请号：EP12849022

申请日：2012-11-14

Applicant: CREE INC

Inventor： ANDREWS PETER SCOTT ,  BRITT JEFFREY CARL

IPC: H01L33/62 ,  H01L23/373 ,  H01L25/075 ,  H01L33/48 ,  H01L33/60 ,  H01L33/64 ,  H05K1/03 ,  H05K3/40

CPC classification number: H01L33/62 ,  H01L23/3735 ,  H01L25/0753 ,  H01L33/60 ,  H01L33/641 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/12032 ,  H05K1/0269 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/16 ,  H05K2201/0338 ,  H05K2201/09036 ,  H05K2201/09227 ,  H05K2201/10106 ,  H05K2201/2054 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Light emitting diode (LED) packages and methods are disclosed herein. In one aspect, a light emitting package is disclosed. The light emitting package includes one or more areas of conductive material having a thickness of less than approximately 50 microns (mum). The package can further include at least one light emitting diode (LED) electrically connected to the conductive material and at least one thin gap disposed between areas of conductive material.