公开(公告)号：JPWO2009119849A1

公开(公告)日：2011-07-28

申请号：JP2010505872

申请日：2009-03-27

Applicant: 京セラ株式会社

Inventor： 前谷　麿明 ,  麿明 前谷

IPC: H05K1/02 ,  H05K1/14

CPC classification number: H05K1/0248 ,  H05K1/0245 ,  H05K1/141 ,  H05K1/147 ,  H05K3/3436 ,  H05K2201/09236 ,  H05K2201/09409 ,  H05K2201/09481 ,  H05K2201/09672

Abstract: 本発明の一実施態様の複合配線基板は、第一線路と、該第一線路よりも長さが長い第二線路と、を備えた第一配線基板と、前記第一線路に電気的に接続される第三線路と、前記第二線路に電気的に接続され、前記第三線路よりも長さが短い第四線路と、を備えた第二配線基板と、を具備する。

公开(公告)号：JP2011129903A

公开(公告)日：2011-06-30

申请号：JP2010269013

申请日：2010-12-02

Applicant: Ibiden Co Ltd ,  イビデン株式会社

Inventor： TAKADA MASATOME ,  NAGAYA FUSAJI ,  OKADA TAKAO ,  MURATA TOMOHIKO

IPC: H05K3/34 ,  H01L23/12 ,  H05K3/00 ,  H05K3/18 ,  H05K3/24 ,  H05K3/28

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/85411 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/28 ,  H05K3/3452 ,  H05K2201/09481 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2203/049 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a printed wiring board which does not generate a short circuit in a bonding pad even if an insulating space is narrowed in arranging the bonding pad. SOLUTION: The top of a conductor circuit covered by a solder resist layer 70 is exposed for the bonding pad 58b, and a nickel layer 73 and a metal layer 74 are formed. In other words, the surface of an interlayer resinous insulating layer 50 with catalysis nucleus created to form an non-electrolytic plating layer 52 is covered with the solder resist layer 70, and neither nickel layer 73 nor metal layer 74 is formed in a resinous layer. Consequently, no short circuit is generated by the nickel layer and the metal layer, and furthermore, the short circuit is not generated in the bonding pad even if the insulating space is narrowed in arranging the bonding pad in a fine pitch. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供即使在布置接合焊盘时绝缘空间变窄时也不会在接合焊盘中产生短路的印刷线路板的制造方法。 解决方案：由阻焊层70覆盖的导体电路的顶部暴露于焊盘58b，形成镍层73和金属层74。 换句话说，形成有形成非电解镀层52的催化核的层间树脂绝缘层50的表面被阻焊层70覆盖，并且镍层73和金属层74都不形成在树脂层中 。 因此，镍层和金属层不产生短路，此外，即使绝缘空间狭窄，接合焊盘的间距变窄，也不会在接合焊盘中产生短路。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011129844A

公开(公告)日：2011-06-30

申请号：JP2009289822

申请日：2009-12-21

Applicant: Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

Inventor： KAWANO MASAYA ,  SOEJIMA KOJI

IPC: H05K3/46

CPC classification number: H05K3/4682 ,  H01L21/4846 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K3/205 ,  H05K3/4644 ,  H05K3/4647 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10545 ,  H05K2201/10674 ,  Y10T29/49155 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To form the conductive connection member of a multi-layer wiring board by a simple procedure. SOLUTION: A multi-layer wiring board 102 is configured such that a wiring layer 110 containing a plurality of vias 114 formed in an insulating film 112 so as to be exposed to the other face side and a wiring layer 130 containing a plurality of vias 138 formed in an insulating film 132 formed on one face side at the opposite side of the other face are laminated. In the multi-layer wiring board 102, each of the plurality of vias 138 formed in the wiring layer 130 is connected directly or via the other conductive materials to any of the vias 114, and each of the plurality of vias 114 is connected directly or via the other conductive materials to any of the vias 138, wherein each of the plurality of vias 114 includes dummy conductive connection members (via 114c, via 114d) which do not configure any current path between the connected via 138 and itself. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：通过简单的步骤形成多层布线板的导电连接构件。 解决方案：多层布线板102被构造成使得包含形成在绝缘膜112中以暴露于另一个面的多个通路114的布线层110和包含多个布线层130的布线层130 形成在形成在另一面的相对侧的一个面侧的绝缘膜132中的通孔138层叠。 在多层布线板102中，形成在布线层130中的多个通孔138中的每一个直接或经由其它导电材料连接到任何通孔114，并且多个通孔114中的每一个直接连接或 通过其它导电材料到通孔138中的任何一个，其中多个通孔114中的每一个都包括虚设的导电连接构件（通孔114c，通孔114d），其不构成连接的通孔138与其本身之间的任何电流路径。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP4619223B2

公开(公告)日：2011-01-26

申请号：JP2005214904

申请日：2005-07-25

Applicant: 新光電気工業株式会社

Inventor： 順一 中村

IPC: H01L23/12 ,  H01L21/60

CPC classification number: H05K3/4007 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15159 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09481 ,  H05K2203/1536 ,  H01L2224/05552

公开(公告)号：JP4605608B2

公开(公告)日：2011-01-05

申请号：JP2007058251

申请日：2007-03-08

Applicant: 南亞電路板股▲ふん▼有限公司

Inventor： 何信芳 ,  林賢傑 ,  江國春 ,  羅興倫

IPC: H05K1/02

CPC classification number: H05K1/0266 ,  H05K1/0268 ,  H05K2201/09481 ,  H05K2201/09927

公开(公告)号：JP2010186848A

公开(公告)日：2010-08-26

申请号：JP2009029463

申请日：2009-02-12

Applicant: Fujitsu Ltd ,  富士通株式会社

Inventor： TAKETOMI NOBUO ,  IRIGUCHI SHIGEO ,  KADOI KAZUHISA ,  HATANAKA KIYOYUKI

IPC: H05K3/46

CPC classification number: H05K3/4617 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/186 ,  H05K3/323 ,  H05K3/341 ,  H05K3/368 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4658 ,  H05K2201/09481 ,  H05K2203/061 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide a structure of an electronic component unit that can suppress thermal effect during manufacture of the electronic component unit and is more resistive to such thermal effect and also provide a method of manufacturing the structure of semiconductor electronic component unit.
SOLUTION: The method of manufacturing the electronic component unit includes a first loading step of reflow loading of an electronic component 50 to a first surface 11 of a base substrate 10, a second loading step of reflow loading of an electronic component 60 of a first surface 21 of a base substrate 20, a first bonding step of bonding a second surface 12 of the base substrate 10 to a first surface 31 of an internal layer substrate 30, and a second bonding step of bonding a second surface 22 of the base substrate 20 to a second surface 32 of the internal layer substrate 30.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种电子部件单元的结构，该电子部件单元能够抑制电子部件单元的制造时的热效应，并且对这种热效应更具抵抗性，并且还提供制造半导体电子部件的结构的方法 单元。 解决方案：制造电子部件单元的方法包括将电子部件50回流到基底基板10的第一表面11的第一加载步骤，第二加载步骤，回流加载电子部件60的电子部件60 基底基板20的第一表面21，将基底10的第二表面12接合到内层基板30的第一表面31的第一接合步骤和将第二接合步骤 基底衬底20连接到内层衬底30的第二表面32.版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010130003A

公开(公告)日：2010-06-10

申请号：JP2009225566

申请日：2009-09-29

Applicant: Samsung Electro-Mechanics Co Ltd ,  サムソン エレクトロ−メカニックス カンパニーリミテッド.

Inventor： KIM KI-HWAN ,  AN JIN-YONG ,  LEE JAE-JOON

IPC: H05K3/46

CPC classification number: H05K3/4007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2203/054 ,  Y10T156/1168

Abstract: PROBLEM TO BE SOLVED: To provide a multi-layer printed circuit board and a manufacturing method thereof, that can prevent curving occurring when a printed circuit board is manufactured. SOLUTION: The manufacturing method includes te steps of: forming an outermost insulation layer, in which openings are formed corresponding to the external contact pads; forming a mask, in which openings are formed corresponding to the external contact pad and a circuit pattern, on the outermost insulation layer; forming the external contact pads and the circuit pattern in the openings of the outermost insulation layer and the openings of the mask; removing the mask; forming a build-up layer by stacking layers over the outermost insulation layer so that the external contact pads and the circuit pattern are covered; forming a first solder resist layer on the build-up layer; forming a second solder resist layer on an opposite side of the outermost insulation layer where the build-up layer is formed; and forming openings in the second solder resist layer so that the external contact pads are exposed. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可以防止在制造印刷电路板时发生弯曲的多层印刷电路板及其制造方法。 解决方案：制造方法包括以下步骤：形成最外绝缘层，其中形成对应于外部接触焊盘的开口; 在最外层绝缘层上形成对应于外部接触焊盘形成开口和电路图案的掩模; 在外绝缘层的开口和掩模的开口中形成外部接触焊盘和电路图案; 去除面膜; 通过在最外层绝缘层上层叠层来形成堆积层，从而覆盖外部接触焊盘和电路图案; 在积层上形成第一阻焊层; 在形成所述积层的所述最外绝缘层的相对侧上形成第二阻焊层; 以及在所述第二阻焊层中形成开口，使得外部接触焊盘露出。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010103519A

公开(公告)日：2010-05-06

申请号：JP2009222738

申请日：2009-09-28

Applicant: Hitachi Chem Co Ltd ,  日立化成工業株式会社

Inventor： TAMURA TADASHI ,  SUGIBAYASHI MANABU ,  SUZUKI KUNIJI ,  HATTORI KIYOO

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4697 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/0959 ,  H05K2201/10515 ,  H05K2203/049 ,  H05K2203/061 ,  H05K2203/063 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a package substrate for mounting a semiconductor element, which has a high degree of freedom in combining packages and a small limitation in pattern design and makes it possible to connect together a top package and a bottom package at a high density in the case of constituting a PoP, and to provide a method for manufacturing the same. SOLUTION: The package substrate for mounting a semiconductor element includes: a cavity layer which is provided with a cavity material and an adhesive and penetrates them; a base layer laminated on the cavity layer by using the adhesive; a cavity section formed by an opening; and a bottomed via hole formed by a through hole. The cavity layer is provided with an inner layer circuit, a metal coating is formed by plating on the inner wall of the bottomed via hole so as to be bonded to the inner layer circuit, and the bottomed via hole is filled with a conductive resin. The method for manufacturing the same is also provided. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于安装半导体元件的封装基板，其具有组合封装的高自由度和图案设计中的小限制，并且使得可以将顶部封装和底部封装 在构成PoP的情况下以高密度，并提供其制造方法。 解决方案：用于安装半导体元件的封装基板包括：空腔层，其设置有空腔材料和粘合剂并穿透它们; 通过使用粘合剂层压在空腔层上的基层; 由开口形成的空腔部分; 以及由通孔形成的有底通孔。 空腔层设置有内层电路，通过在底层通孔的内壁上电镀形成金属涂层，从而与内层电路接合，底面的通孔填充有导电树脂。 还提供了其制造方法。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010103518A

公开(公告)日：2010-05-06

申请号：JP2009222737

申请日：2009-09-28

Applicant: Hitachi Chem Co Ltd ,  日立化成工業株式会社

Inventor： TAMURA TADASHI ,  SUGIBAYASHI MANABU ,  SUZUKI KUNIJI ,  MASAKI TAKASHI

IPC: H05K3/46 ,  H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H05K1/183 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4697 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2203/049 ,  H05K2203/061 ,  H05K2203/063 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a package substrate for mounting a semiconductor element, which has a high degree of freedom in combining packages and a small limitation in pattern design and makes it possible to connect together a top package and a bottom package at a high density in the case of constituting a PoP, and to provide a method for manufacturing the same by simple processes at a low cost. SOLUTION: The package substrate for mounting a semiconductor element includes: a cavity layer having an opening and a through hole; a base layer laminated on the cavity layer; a cavity section formed by the opening; and a bottomed via hole formed by the through hole. The package substrate for mounting a semiconductor element has a metal film which is formed by forming a metal coating on the inner wall of the bottomed via hole, filling the bottomed via hole with a conductive resin with the metal coating as a base, arranging a conductive component contained in the conductive resin in an exposed state on the entrance side of the bottomed via hole, and directly depositing plating on the exposed conductive component. The method for manufacturing the same is also provided. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于安装半导体元件的封装基板，其具有组合封装的高自由度和图案设计中的小限制，并且使得可以将顶部封装和底部封装 在构成PoP的情况下以高密度，并且通过简单的方法以低成本提供其制造方法。 解决方案：用于安装半导体元件的封装基板包括：具有开口和通孔的空腔层; 层叠在空腔层上的基层; 由所述开口形成的空腔部; 以及由通孔形成的有底通孔。 用于安装半导体元件的封装基板具有金属膜，该金属膜通过在有底通孔的内壁上形成金属涂层而形成，用带有金属涂层的导电树脂作为基底填充有底通孔， 在底部通孔的入口侧处于暴露状态的导电树脂中所含的成分，并且在暴露的导电性部件上直接镀覆电镀。 还提供了其制造方法。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010003749A

公开(公告)日：2010-01-07

申请号：JP2008159298

申请日：2008-06-18

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OIKAWA HARUTOSHI ,  KIMURA KIYOHIRO

IPC: H05K1/02 ,  G06F3/041 ,  G06F3/045 ,  H05K1/14

CPC classification number: H05K3/361 ,  H05K3/281 ,  H05K3/323 ,  H05K3/421 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2203/1572

Abstract: PROBLEM TO BE SOLVED: To provide a flexible printed wiring board thinner than a conventional one, and also to provide a touch panel, a display panel, and a display, each having the printed wiring board. SOLUTION: A wiring layer 33 is arranged so that it is brought into contact with only one face of a base film 31. An anisotropic conductive film 35 installed on one face of the base film 31 is electrically connected to two wiring layers 32 which are installed on one face of the base film 31 and whose openings are not confronted each other. An anisotropic conductive film 36 arranged on the other face of the base film 31 is electrically connected to the two wiring layers 32 which are installed on one face of the base film 31 through an opening 31A formed in the base film 31 such that their openings confront each other. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供比常规的柔性印刷线路板更薄的柔性印刷线路板，并且还提供具有印刷线路板的触摸面板，显示面板和显示器。 解决方案：布线层33布置成仅与底膜31的一个面接触。安装在基膜31的一个面上的各向异性导电膜35电连接到两个布线层32 其安装在基膜31的一个面上，并且其开口彼此不相对。 布置在基膜31的另一面上的各向异性导电膜36电连接到两个布线层32，两个布线层32通过形成在基膜31中的开口31A安装在基膜31的一个面上，使得它们的开口面向 彼此。 版权所有（C）2010，JPO＆INPIT