公开(公告)号：US08466997B2

公开(公告)日：2013-06-18

申请号：US12651304

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H04N5/225 ,  H05K7/00 ,  H01L23/06

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An optical sensor package has a transparent substrate with a redistribution layer formed on a face thereof, which includes a window and a plurality of electrically conductive traces. A semiconductor substrate, including an optical sensor and a plurality of contact terminals on a face thereof, is positioned on the transparent substrate in a face-to-face arrangement, with the optical sensor directly opposite the window, and with each of the contact terminals electrically coupled to a respective one of the electrically conductive terminals. The transparent substrate has larger overall dimensions than the semiconductor substrate, so that one or more edges of the transparent substrate extend beyond the corresponding edges of the semiconductor substrate. A plurality of solder balls are positioned on the face of the transparent substrate, each in electrical contact with a respective one of the electrically conductive terminals. The solder balls and the semiconductor substrate are at least partially encapsulated in an encapsulating layer formed on the face of the transparent substrate, which has been planarized to expose upper portions of the solder balls, as contact pads of the optical sensor package.

Abstract translation: 光学传感器封装具有在其表面上形成有再分布层的透明衬底，其包括窗口和多个导电迹线。 包括光学传感器和其表面上的多个接触端子的半导体衬底以与光学传感器直接相对的窗口面对面布置在透明衬底上，并且每个接触端子 电耦合到相应的一个导电端子。 透明基板具有比半导体基板更大的总体尺寸，使得透明基板的一个或多个边缘延伸超过半导体基板的对应边缘。 多个焊球定位在透明基板的表面上，每个焊球与相应的导电端子电接触。 焊球和半导体衬底至少部分地封装在形成在透明衬底的已被平坦化以暴露焊球上部的表面上的封装层中，作为光学传感器封装的接触焊盘。

公开(公告)号：US20130127041A1

公开(公告)日：2013-05-23

申请号：US13302602

申请日：2011-11-22

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L23/485 ,  B23K31/02 ,  B23K1/20

CPC classification number: H01L24/97 ,  B23K1/0016 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package.

Abstract translation: 提供球栅阵列引脚网格阵列转换方法。 示例性方法可以包括将多个焊球耦合到相应的多个引脚栅极阵列接触焊盘。 多个焊球中的每一个被封装在固定材料中。 多个焊球的一部分和固定材料的一部分被去除以提供多个暴露的焊球。 暴露的焊球被软化，并且多个销构件中的每一个插入软化的暴露的焊球中。 多个销构件形成销栅格阵列封装。

公开(公告)号：US20110156240A1

公开(公告)日：2011-06-30

申请号：US12651362

申请日：2009-12-31

Applicant: Jing-En Luan ,  Kim-Yong Goh

Inventor： Jing-En Luan ,  Kim-Yong Goh

IPC: H01L23/488 ,  H01L21/78 ,  H01L21/60

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/03 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A fan-out wafer level package includes a semiconductor die with contact pads positioned on a top surface. A fan-in redistribution layer positioned over the die includes contact pads in electrical communication with the first contact pads of the die. A buffer layer positioned over the fan-in layer includes a plurality of vias, in electrical contact with the contact pads of the fan-in layer. A fan-in redistribution layer is positioned over the buffer layer and includes contact pads on a surface opposite the buffer layer, in electrical communication with the vias. The semiconductor die, fan-in layer, and buffer layer are encapsulated in a molding com-pound layer. Solder contacts, for electrically connecting the semiconductor device to a electronic circuit board, are positioned on contact pads of the fan-out layer. The buffer layer has a substantial thickness, to reduce and distribute shear stresses resulting from thermal mismatch of coefficients of thermal expansion of the semiconductor die and a circuit board.

Abstract translation: 扇形晶片级封装包括具有位于顶表面上的接触焊盘的半导体管芯。 位于管芯上方的扇形重分布层包括与管芯的第一接触垫电连通的接触焊盘。 位于扇入层之上的缓冲层包括与扇入层的接触垫电接触的多个通孔。 风扇再分配层位于缓冲层上方，并且包括与通孔相通的与缓冲层相对的表面上的接触焊盘。 将半导体管芯，扇入层和缓冲层封装在成型层中。 用于将半导体器件电连接到电子电路板的焊接触点位于扇出层的接触焊盘上。 缓冲层具有相当大的厚度，以减少和分配由半导体管芯和电路板的热膨胀系数的热失配导致的剪切应力。

公开(公告)号：US07956475B2

公开(公告)日：2011-06-07

申请号：US12336273

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/28

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/49816 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder balls may be set out by rows and columns. A plurality of wires electrically connect the semiconductor chip to the solder balls. A layer of encapsulating compound is deposited over the semiconductor chip. A step cavity of a selected depth and shape is formed in the layer of encapsulating compound at or near the edge or periphery of the layer of encapsulating compound. The step cavity is separated from the solder balls by the substrate layer but spans over a plurality of selected solder balls.

Abstract translation: 球栅阵列（BGA）封装包括具有第一侧和第二侧的衬底层。 半导体芯片通过介电粘合剂层附接到基板层的第一侧。 多个焊球附着在基板层的第二面上。 焊球可以由行和列排列。 多个电线将半导体芯片电连接到焊球。 一层封装化合物沉积在半导体芯片上。 在密封化合物层的边缘或周边处或附近，在封装化合物层中形成所选择的深度和形状的台阶腔。 阶跃腔通过衬底层与焊球分离，但跨越多个选定的焊球。

公开(公告)号：US08502394B2

公开(公告)日：2013-08-06

申请号：US12651080

申请日：2009-12-31

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: A multi-stack semiconductor dice assembly has enhanced board-level reliability and integrated electrical functionalities over a common package foot-print. The multi-stack semiconductor dice assembly includes a bottom die having a stepped upper surface. The stepped upper surface includes a base region and a stepped region, which is raised relative to the base region. The base region includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls. An upper die is stacked above the bottom die. The upper die includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls and are arranged to align with the attachment structures of the bottom die. Electrically conductive balls are attached to the attachment structures of the bottom die and the attachment structures of the upper die.

Abstract translation: 多堆叠半导体晶片组件在普通封装脚印上增强了板级可靠性和集成电气功能。 多层半导体晶片组件包括具有阶梯状上表面的底模。 台阶状上表面包括基部区域和相对于基底区域升高的阶梯状区域。 基部区域包括多个附接结构，其尺寸和形状被容纳以接纳导电球。 上模具堆叠在底模上方。 上模具包括多个附接结构，其尺寸和形状适于容纳导电球，并且被布置成与底模的附接结构对准。 导电球连接到底模的附接结构和上模的附接结构。

公开(公告)号：US20130161806A1

公开(公告)日：2013-06-27

申请号：US13335467

申请日：2011-12-22

Applicant: Xueren ZHANG ,  Kim-Yong GOH ,  Wingshenq WONG

Inventor： Xueren ZHANG ,  Kim-Yong GOH ,  Wingshenq WONG

IPC: H01L23/495 ,  H05K5/02 ,  H05K13/04 ,  H01L21/50

CPC classification number: H01L24/78 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/14 ,  H01L2924/3025 ,  Y10T29/53265 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.

Abstract translation: 一种用于在各种包装方法步骤期间最小化可能危及引线框安装件到集成电路管芯封装中的支撑结构的力的装置和方法。 当使用窗夹来在包装期间在引线框接合步骤期间或在引线接合步骤期间提供压力时，由窗夹具施加的垂直力可以通过支撑结构的顶板的物理轮廓在横向方向上传递 。 通过改变支撑结构的顶板的物理轮廓，例如通过设置特定类型的轮廓突起，可以最小化或消除作用于实现引线框架与支撑结构的牢固结合的侧向力。 此外，在引线接合期间，相同的最小化或消除侧向力导致改善的引线接合。

公开(公告)号：US20130147052A1

公开(公告)日：2013-06-13

申请号：US13313397

申请日：2011-12-07

Applicant: Xueren Zhang ,  Kim-Yong Goh

Inventor： Xueren Zhang ,  Kim-Yong Goh

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/563 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05092 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05681 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/13027 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.

Abstract translation: 集成电路管芯具有位于集成电路管芯上的所有接触焊盘上的电介质层。 在集成电路管芯的每个接触焊盘上的介电层中设置开口，以便允许在集成电路和管芯外部的电路板之间进行电耦合。 对于位于管芯的中心区域的接触焊盘，电介质层中的开口位于接触焊盘的中心区域。 对于那些位于模具周边区域的接触垫，邻近周边模具间隔开，电介质层中的开口偏离接触焊盘的中心，并且位于比芯片中心更靠近模具的中心区域 接触垫是到模具的中心区域。

公开(公告)号：US20130147024A1

公开(公告)日：2013-06-13

申请号：US13324799

申请日：2011-12-13

Applicant: Kim-Yong GOH ,  Xueren Zhang ,  Wingshenq Wong

Inventor： Kim-Yong GOH ,  Xueren Zhang ,  Wingshenq Wong

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/13 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49861 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion.

Abstract translation: 集成电路封装结构包括具有空腔的底部，连接到阶梯腔的顶表面的集成电路，附接到底部的引线框架，用于将集成电路电耦合到引线框架的引线接合部以及顶部部分 保形地覆盖集成电路和底部。

公开(公告)号：US20120178213A1

公开(公告)日：2012-07-12

申请号：US13424610

申请日：2012-03-20

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L21/60

CPC classification number: H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract translation: 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。

公开(公告)号：US20110157452A1

公开(公告)日：2011-06-30

申请号：US12651304

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H04N5/225 ,  H01L33/00 ,  H01L31/00

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An optical sensor package has a transparent substrate with a redistribution layer formed on a face thereof, which includes a window and a plurality of electrically conductive traces. A semiconductor substrate, including an optical sensor and a plurality of contact terminals on a face thereof, is positioned on the transparent substrate in a face-to-face arrangement, with the optical sensor directly opposite the window, and with each of the contact terminals electrically coupled to a respective one of the electrically conductive terminals. The transparent substrate has larger overall dimensions than the semiconductor substrate, so that one or more edges of the transparent substrate extend beyond the corresponding edges of the semiconductor substrate. A plurality of solder balls are positioned on the face of the transparent substrate, each in electrical contact with a respective one of the electrically conductive terminals. The solder balls and the semiconductor substrate are at least partially encapsulated in an encapsulating layer formed on the face of the transparent substrate, which has been planarized to expose upper portions of the solder balls, as contact pads of the optical sensor package.

Abstract translation: 光学传感器封装具有在其表面上形成有再分布层的透明衬底，其包括窗口和多个导电迹线。 包括光学传感器和其表面上的多个接触端子的半导体衬底以与光学传感器直接相对的窗口面对面布置在透明衬底上，并且每个接触端子 电耦合到相应的一个导电端子。 透明基板具有比半导体基板更大的总体尺寸，使得透明基板的一个或多个边缘延伸超过半导体基板的对应边缘。 多个焊球定位在透明基板的表面上，每个焊球与相应的导电端子电接触。 焊球和半导体衬底至少部分地封装在形成在透明衬底的已被平坦化以暴露焊球上部的表面上的封装层中，作为光学传感器封装的接触焊盘。