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    OFDM demodulation method and semiconductor integrated circuit device
    1.
    发明申请
    OFDM demodulation method and semiconductor integrated circuit device 有权
    OFDM解调方法和半导体集成电路器件

    公开(公告)号：US20040264432A1

    公开(公告)日：2004-12-30

    申请号：US10809898

    申请日：2004-03-26

    Applicant: Renesas Technology Corp.

    Inventor： Toyokazu Hori ,  Hiroshi Nogami ,  Toshihito Habuka ,  Naoto Inokawa ,  Kazuyuki Takada

    IPC: H04J001/00

    CPC classification number: H04L25/061 ,  H04L27/2657 ,  H04L27/2675 ,  H04L27/2679

    Abstract: The invention comprises: processing for receiving an OFDM packet having a preamble and the following data transmission symbol, in which packet the subcarrier interval of the preamble is set wider than that of the data transmission symbol; processing for estimating a DC offset occurring at a receiving side by using the received preamble; processing for correcting the DC offset on the received data transmission symbol, according to the estimation result of the DC offset; and processing for demodulating the DC offset corrected data transmission symbol. Thus, it is possible to estimate a DC offset and then correct the DC offset according to the estimated value, in the OFDM packet with no nul symbol defined there.

    Abstract translation: 本发明包括：接收具有前同步码和后续数据传输符号的OFDM分组的处理，其中前导码的子载波间隔被设置为比数据传输符号的子载波间隔宽; 用于通过使用所接收的前导码来估计在接收侧发生的DC偏移的处理; 根据直流偏移的估计结果对接收到的数据传输符号校正直流偏移的处理; 以及用于解调DC偏移校正数据传输符号的处理。 因此，可以估计DC偏移，然后根据估计值在没有nul符号的OFDM分组中校正DC偏移。

    Nonvolatile memory and method of restoring of failure memory cell
    2.
    发明申请
    Nonvolatile memory and method of restoring of failure memory cell 失效
    非易失性存储器和故障存储器单元的恢复方法

    公开(公告)号：US20040264245A1

    公开(公告)日：2004-12-30

    申请号：US10767627

    申请日：2004-01-30

    Applicant: Renesas Technology Corp.

    Inventor： Ken Matsubara ,  Takayuki Tamura ,  Tomoyuki Fujisawa

    IPC: G11C016/04

    CPC classification number: G11C16/225

    Abstract: An electrically writable/erasable nonvolatile semiconductor memory such as an AND-type or NOR-type flash memory having an array structure, in which numerous memory cells are connected in parallel between common bit lines and source lines, is capable of readily detecting a memory cell in depletion failure which occurs in the event of a power supply cutoff during a memory cell threshold voltage shift-down operation by the writing or erasing operation. In operation, at the entry of a certain command or at the time of power-on, all word lines are unselected and bit line selecting switches are turned on to find the presence of a memory cell having a current flow due to depletion failure with sense amplifiers connected to the bit lines. On finding the presence of a failing cell, a voltage of selection level (VSS or negative voltage) is applied to each word line in turn, with remaining word lines being pulled to an unselection voltage level (negative voltage or VSS).

    Semiconductor device and a method of manufacturing the same
    4.
    发明申请
    Semiconductor device and a method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20040262678A1

    公开(公告)日：2004-12-30

    申请号：US10827295

    申请日：2004-04-20

    Applicant: Renesas Technology Corp.

    Inventor： Yoshito Nakazawa ,  Yuji Yatsuda

    IPC: H01L029/74

    CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, pnull type semiconductor region and pnull type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the nnull type single crystal silicon layer 1B is null (nullnullcm), the CHSP is set to satisfy the following equation: CHSPnull3.80null0.148null.

    Abstract translation: 实现沟槽栅型功率MISFET的击穿电压的升高而不增加制造步骤的数量。 在根据本发明的半导体器件的制造方法中，在一个杂质离子注入步骤中同时在栅极线区域中形成p +型半导体区域和p +型场限制环，以使它们进入 与其中形成有栅极引出电极的沟槽接触。 在形成时，假设设置在凹槽外侧的栅极引出电极的宽度为CHSP，并且n +型单晶硅层1B的电阻率为rho（Ω·cm），则将CHSP设定为满足以下 方程式：CHSP <= 3.80 + 0.148rho。

    Semiconductor memory device permitting boundary scan test
    6.
    发明申请
    Semiconductor memory device permitting boundary scan test 审中-公开
    半导体存储器允许边界扫描测试

    公开(公告)号：US20040250165A1

    公开(公告)日：2004-12-09

    申请号：US10649682

    申请日：2003-08-28

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Tetsushi Tanizaki

    IPC: H02H003/05

    CPC classification number: G11C29/48 ,  G11C2029/3202

    Abstract: A boundary scan cell in a semiconductor memory device (memory core) is provided corresponding to each terminal for performing a boundary scan test. A test controller and a read/write control circuit cause the boundary scan cell to latch input write data in a late write operation, until a next write cycle of the write cycle at which the write data was input from the terminal.

    Abstract translation: 半导体存储器件（存储器核心）中的边界扫描单元对应于每个用于执行边界扫描测试的端子被提供。 测试控制器和读/写控制电路使得边界扫描单元在迟写操作中锁存输入写入数据，直到写入数据从终端输入的写周期的下一个写周期为止。

    Microcomputer having power supply circuit switching low pass filter
    7.
    发明申请
    Microcomputer having power supply circuit switching low pass filter 审中-公开
    微电脑具有电源电路切换低通滤波器

    公开(公告)号：US20040250143A1

    公开(公告)日：2004-12-09

    申请号：US10786588

    申请日：2004-02-26

    Applicant: Renesas Technology Corp.

    Inventor： Michiaki Kuroiwa

    IPC: G06F001/26

    CPC classification number: G06F1/26 ,  G06F1/08 ,  G06F1/305

    Abstract: In a flash memory write mode, a microcomputer operation mode setting circuit sets a mode setting signal at one level. At this stage, a voltage drop caused by an LPF formed of a resistor, an inductor, and a capacitor can be suppressed at a low level. In a mode other than the flash memory write mode, the microcomputer operation mode setting circuit sets the mode setting signal at another level. At this stage, high frequency noise can be removed by the LPF formed of the resistor, the inductor, and the capacitor.

    Abstract translation: 在闪存写入模式中，微机操作模式设置电路将模式设置信号设置在一个级别。 在这个阶段，由电阻器，电感器和电容器形成的LPF引起的电压降可以被抑制在低水平。 在闪存写入模式以外的模式中，微型计算机操作模式设置电路将模式设置信号设置在另一个级别。 在这个阶段，由电阻器，电感器和电容器形成的LPF可以去除高频噪声。

    Semiconductor memory device capable of controlling potential level of power supply line and/or ground line
    8.
    发明申请
    Semiconductor memory device capable of controlling potential level of power supply line and/or ground line 有权
    能够控制电源线和/或接地线的电位的半导体存储器件

    公开(公告)号：US20040246805A1

    公开(公告)日：2004-12-09

    申请号：US10689344

    申请日：2003-10-21

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Koji Nii

    IPC: G11C005/00

    CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C11/413

    Abstract: Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.

    Abstract translation: 电平控制信号都设置为H电平，电源线的电位都设置为低于电源电位。 以这种方式，可以显着地减少存储单元阵列的等待和写入操作期间的栅极泄漏电流。 电平控制信号分别设置为L电平和H电平，并且仅一个电源线的电位被设置为低于电源电位。 以这种方式，可以减少在存储单元阵列的读取操作期间的功耗。

    Data processing device and mobile device
    9.
    发明申请
    Data processing device and mobile device 有权
    数据处理设备和移动设备

    公开(公告)号：US20040243877A1

    公开(公告)日：2004-12-02

    申请号：US10827288

    申请日：2004-04-20

    Applicant: Renesas Technology Corp.

    Inventor： Kazuo Sakamoto ,  Naozumi Morino ,  Ikuo Kudo

    IPC: G06F001/04

    CPC classification number: G06F5/06 ,  G06F1/10

    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

    Abstract translation: 即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。 在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路， 与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号 存储卡。

    Nonvolatile memory device
    10.
    发明申请
    Nonvolatile memory device 有权
    非易失性存储器件

    公开(公告)号：US20040241944A1

    公开(公告)日：2004-12-02

    申请号：US10878247

    申请日：2004-06-29

    Applicant: Renesas Technology Corp.

    Inventor： Kozo Katayama ,  Yoshiaki Kamigaki ,  Shinichi Minami

    IPC: G11C011/34

    CPC classification number: H01L27/115 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L29/7923

    Abstract: Disclosed herein is a nonvolatile memory device having a plurality of nonvolatile memory cells. In the nonvolatile memory cell, a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side so that each of the memory cells stores information therein. The memory gate electrode and the switch gate electrodes extend in the same direction. Thus, even if a high voltage is applied to the memory gate electrode of each write-intended memory cell which uses the memory gate electrode and switch gate electrodes in common, and write and write blocking voltages are applied through the first and second signal electrodes, each memory cell intended for write non-selection can avoid the application of a high electric field thereto owing to the switch gate electrodes held in a cut-off state.

    Abstract translation: 这里公开了具有多个非易失性存储单元的非易失性存储器件。 在非易失性存储单元中，在栅极绝缘膜和介于其间的栅极氮化物膜的第一半导体区域上形成存储栅电极。 第一和第二开关栅电极以及用作源/漏电极的第一和第二信号电极形成在存储栅电极的两侧。 从源极将电子注入到栅极氮化物膜中，使得每个存储单元在其中存储信息。 存储栅电极和开关栅电极沿相同方向延伸。 因此，即使对共用存储栅电极和开关栅电极的每个写入型存储单元的存储栅电极施加高电压，并且通过第一和第二信号电极施加写和写分断电压， 用于写入不选择的每个存储单元可以避免由于开关栅电极保持在截止状态而向其施加高电场。

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