公开(公告)号：US20150287824A1

公开(公告)日：2015-10-08

申请号：US14244322

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shishir Ray ,  Jin Ping Liu ,  Bharat Krishnan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L21/268 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L21/268 ,  H01L21/26513 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L29/7847

Abstract: Integrated circuits with stressed semiconductor substrates, processes for preparing stressed semiconductor substrates, and processes for preparing integrated circuits including stressed semiconductor substrates are provided herein. An exemplary process for preparing a stressed semiconductor substrate includes providing a semiconductor substrate of a semiconductor material having a first crystalline lattice constant; introducing a dopant on and into a surface layer of the semiconductor substrate via ion implantation at an amount above a solubility limit of the dopant in the semiconductor material to form a dopant-containing surface layer of the semiconductor substrate; applying energy to the dopant-containing surface layer of the semiconductor substrate with an ultra-short pulse laser to form a molten semiconductor:dopant layer on a surface of the semiconductor substrate; and removing the energy such that the molten semiconductor:dopant layer forms a solid semiconductor:dopant layer with a second crystalline lattice having a second lattice constant that differs from the first lattice constant.

Abstract translation: 具有应力半导体衬底的集成电路，制备受压半导体衬底的工艺，以及制备包括应力半导体衬底的集成电路的工艺。 制备应力半导体衬底的示例性方法包括提供具有第一晶格常数的半导体材料的半导体衬底; 在半导体材料中以高于掺杂剂的溶解度极限的量经由离子注入在半导体衬底的表面层上引入掺杂剂，以形成半导体衬底的掺杂剂表面层; 用超短脉冲激光对半导体衬底的掺杂剂表面层施加能量，以在半导体衬底的表面上形成熔融半导体：掺杂剂层; 并且去除能量，使得熔融半导体：掺杂剂层形成固体半导体：具有与第一晶格常数不同的第二晶格常数的第二晶格的掺杂剂层。

公开(公告)号：US09882052B2

公开(公告)日：2018-01-30

申请号：US15197892

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Judson Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James McArdle ,  Murat Kerem Akarvardar

IPC: H01L21/335 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US09165767B2

公开(公告)日：2015-10-20

申请号：US14071170

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jody A. Fronheiser ,  Jinping Liu ,  Bongki Lee

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延生长在增加的（100）区域。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长附加外延的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并，同时 也增加了他们的体积。

公开(公告)号：US20180130656A1

公开(公告)日：2018-05-10

申请号：US15843649

申请日：2017-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson Robert Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James Mcardle ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US09287180B2

公开(公告)日：2016-03-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US09093476B2

公开(公告)日：2015-07-28

申请号：US13954289

申请日：2013-07-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括：具有第一侧，第二侧，暴露的第一端面和暴露的第二端面的翅片结构的沟道区。 形成在沟道区域的第一侧和第二侧上方的栅极。 该方法包括通过暴露的第一端表面和暴露的第二端表面将离子注入沟道区域。 此外，所述方法包括在所述通道区域的暴露的第一端面和暴露的第二端面附近形成所述鳍结构的源极/漏极区域。

公开(公告)号：US10056458B2

公开(公告)日：2018-08-21

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho Maeng ,  Andy Wei ,  Anthony Ozzello ,  Bharat Krishnan ,  Guillaume Bouche ,  Haifeng Sheng ,  Haigou Huang ,  Huang Liu ,  Huy M. Cao ,  Ja-Hyung Han ,  SangWoo Lim ,  Kenneth A. Bates ,  Shyam Pal ,  Xintuo Dai ,  Jinping Liu

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20170033178A1

公开(公告)日：2017-02-02

申请号：US14813254

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bharat Krishnan ,  Shishir Ray ,  Jinping Liu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/763 ,  H01L21/02164 ,  H01L21/02345 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/76882 ,  H01L21/76883 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.

Abstract translation: 提供了集成电路及其制造方法。 根据一个实施例，制造集成电路的方法包括形成由第一材料限定的沟槽。 沟槽填充有第二材料以产生限定在第二材料内的间隙，其中第二材料处于固态。 第二材料在沟槽内回流以减小间隙的体积，然后第二材料在沟槽内固化。

公开(公告)号：US09559166B2

公开(公告)日：2017-01-31

申请号：US14609504

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shishir Ray ,  Bharat Krishnan ,  Min-hwa Chi

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L29/04 ,  H01L21/268

CPC classification number: H01L29/0847 ,  H01L21/268 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.

Abstract translation: 提供制造具有至少一个具有应力部分的源极区或漏极区的晶体管的方法。 所述方法包括：在衬底结构的空腔内形成具有内部应力的至少一个源极区域或漏极区域; 以及重新铺展所述至少一个源极区域或漏极区域以减少所述至少一个源极区域或漏极区域的表面缺陷，而不放松其应力部分。 例如，表面重排可以包括熔化至少一个源区或漏区的上部。 另外，重新表面可以包括重新结晶至少一个源区或漏区的上部，和/或向至少一个源区或漏区提供至少一个{111}表面。

公开(公告)号：US09059218B2

公开(公告)日：2015-06-16

申请号：US14030506

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jinping Liu ,  Zhao Lun ,  Hui Zhan ,  Bongki Lee

IPC: H01L21/22 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/6681 ,  H01L21/2253 ,  H01L21/2652 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.

Abstract translation: 半导体结构包括设置在有源区上的半导体衬底，有源区和伪栅极结构。 在伪栅极结构和有源区域上设置包括底部氧化物层和顶部氮化物层的牺牲保形层，以在源极和漏极注入期间保护虚拟栅极。 使用诸如n型掺杂剂或p型掺杂剂的掺杂剂注入有源区域，以在有源区域中产生源极区域和漏极区域，之后去除牺牲保形层。