公开(公告)号：US09923082B2

公开(公告)日：2018-03-20

申请号：US15453939

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US20170287829A1

公开(公告)日：2017-10-05

申请号：US15085077

申请日：2016-03-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arvind Kumar ,  Murshed M. Chowdhury ,  Brian J. Greene ,  Chung-Hsun Lin

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/08 ,  H01L23/535 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/381

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

公开(公告)号：US09508826B2

公开(公告)日：2016-11-29

申请号：US14307575

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/84 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L29/66545 ,  H01L21/02107 ,  H01L21/28132 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.

公开(公告)号：US09418903B2

公开(公告)日：2016-08-16

申请号：US14283633

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl Radens

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/308 ,  H01L21/3083 ,  H01L27/1211 ,  H01L29/66818

Abstract: Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as SRAM design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (Vt) for a part of the fin, rendering that part of the fin electrically inactive, which changes the effective device width (Weff). Other fins are unclad, and provide maximum area of constant threshold voltage. In this way, the effective device width of some devices is reduced. Therefore, the effective device width is controllable by controlling the level of cladding of the fin.

Abstract translation: 本发明的实施例提供了通过引入分数有效装置宽度可以放宽有效宽度的固有离散化的方法和结构，从而为诸如SRAM设计优化的设计应用提供了更大的灵活性。 一些翅片的一部分用覆盖层或功函材料包覆以改变鳍的一部分的阈值电压（Vt），使得该部分鳍电活动，这改变了有效器件宽度（Weff）。 其他翅片不包括，并提供最大面积的恒定阈值电压。 以这种方式，某些设备的有效设备宽度就会降低。 因此，通过控制翅片的包层水平来控制有效的装置宽度。

公开(公告)号：US09412759B2

公开(公告)日：2016-08-09

申请号：US14566779

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/311 ,  H01L21/84 ,  H01L21/28

CPC classification number: H01L27/1211 ,  H01L21/28017 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653

Abstract: A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.

Abstract translation: 通过增加栅极接触和栅极结构的栅极导电部分之间的接触面积来提供具有降低的接触电阻的栅极接触。 栅极接触形成与栅极导电部分的一部分的最顶表面和最外侧壁的至少部分的直接接触，从而增加了栅极接触和栅极结构之间的接触面积。 通过用栅极接触完全围绕栅极结构的栅极导电部分的一部分，可以进一步提高本申请的栅极接触面积。

公开(公告)号：US20160218222A1

公开(公告)日：2016-07-28

申请号：US15089647

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

公开(公告)号：US09269786B2

公开(公告)日：2016-02-23

申请号：US14037423

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I-Chih Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Claude Ortolland ,  Kai Zhao

IPC: H01L29/76 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.

Abstract translation: 使用替代金属栅极（RMG）制造的标准高K金属栅极（HKMG）CMOS技术也被称为最终集成流，易受氧进入高K栅介质层和氧气扩散入栅极 电介质和半导体沟道区。 栅极电介质和半导体沟道界面处的氧会引起不必要的氧化物再生长，导致有效的氧化物厚度增加，并且晶体管阈值电压偏移，这两者都是高度可变的并且降低半导体芯片性能。 通过引入在低温下沉积的氮化硅，在金属栅极形成之后，可以避免氧进入和栅介质再生长，并且保持高的半导体芯片性能。

公开(公告)号：US09524986B2

公开(公告)日：2016-12-20

申请号：US14315362

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Ramachandra Divakaruni ,  Judson R. Holt ,  Arvind Kumar ,  Unoh Kwon

IPC: H01L21/02 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L21/306 ,  H01L21/311 ,  H01L29/16 ,  H01L21/3105

CPC classification number: H01L27/1207 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.

Abstract translation: 本发明一般涉及半导体器件，更具体地说，涉及通过捕获外延期间发生的晶格位错而在绝缘体上硅绝缘体（SOI）衬底上形成高迁移率鳍状场效应晶体管（finFET）鳍的结构和方法 在半导体层中形成的凹部中生长。 结晶晶格位错可以保留在薄的隔离层下方，从而减少器件厚度以及高纵横比蚀刻和鳍形成的需要。

公开(公告)号：US09484246B2

公开(公告)日：2016-11-01

申请号：US14307604

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee ,  Richard A. Wachnik

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/84 ,  H01L21/74 ,  H01L27/12

CPC classification number: H01L21/76283 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally surrounding a portion of the buried conductive layer is formed, and is filled with at least a dielectric liner to form a deep capacitor trench isolation structure. Contact via structures are formed through the buried insulator layer and a top semiconductor layer and onto the portion of the buried conductive layer, which constitutes a buried conductive conduit. The deep capacitor trench isolation structure may be formed concurrently with at least one deep trench capacitor. A patterned portion of the top semiconductor layer may be employed as an additional conductive conduit for signal transmission. Further, the deep capacitor trench isolation structure may include a conductive portion, which can be electrically biased to control the impedance of the signal path including the buried conductive conduit.

Abstract translation: 在绝缘体上半导体（SOI）衬底的掩埋绝缘体层下方形成掩埋导电层。 形成横向围绕埋入导电层的一部分的深隔离沟槽，并且至少填充有介电衬垫以形成深电容器沟槽隔离结构。 通过结构的接触通过掩埋绝缘体层和顶部半导体层形成，并且形成在掩埋导电层的构成掩埋导电导管的部分上。 深电容器沟槽隔离结构可以与至少一个深沟槽电容器同时形成。 可以使用顶部半导体层的图案化部分作为用于信号传输的附加导电管道。 此外，深电容器沟槽隔离结构可以包括导电部分，导电部分可被电偏置以控制包括埋入导电导管的信号路径的阻抗。

公开(公告)号：US20160172378A1

公开(公告)日：2016-06-16

申请号：US14566779

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L27/12 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/28017 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653

Abstract: A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.

Abstract translation: 通过增加栅极接触和栅极结构的栅极导电部分之间的接触面积来提供具有降低的接触电阻的栅极接触。 栅极接触形成与栅极导电部分的一部分的最顶表面和最外侧壁的至少部分的直接接触，从而增加了栅极接触和栅极结构之间的接触面积。 通过用栅极接触完全围绕栅极结构的栅极导电部分的一部分，可以进一步提高本申请的栅极接触面积。