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    ADJUSTING OF PATTERNS IN DESIGN LAYOUT FOR OPTICAL PROXIMITY CORRECTION
    1.
    发明申请
    ADJUSTING OF PATTERNS IN DESIGN LAYOUT FOR OPTICAL PROXIMITY CORRECTION 有权

    公开(公告)号：US20180052388A1

    公开(公告)日：2018-02-22

    申请号：US15239072

    申请日：2016-08-17

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sudeep Mandal ,  Arun S. Mampazhy

    IPC: G03F1/36 ,  G06F17/50

    CPC classification number: G03F1/36 ,  G06F17/5081

    Abstract: Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first pattern positioned adjacent to a second pattern, wherein an OPC modeling rule of the IC design layout prohibits the first pattern from being adjusted, and wherein the second pattern does not reduce a printability metric of the first pattern; adjusting the design of the second pattern to reduce at least one printing error in the first pattern, wherein a functionality of the second pattern in the IC design layout is unchanged after the adjusting; and implementing OPC on the IC design layout including the target region with the adjusted second pattern therein.

    Controlling right-of-way for priority vehicles
    3.
    发明授权
    Controlling right-of-way for priority vehicles 有权

    公开(公告)号：US10049570B2

    公开(公告)日：2018-08-14

    申请号：US14918776

    申请日：2015-10-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric A. Foreman ,  Sudeep Mandal

    IPC: G08G1/0965 ,  G01C21/34 ,  G08G1/087 ,  G01C21/36

    Abstract: Various embodiments include approaches for analyzing a set of travel pathways for a priority vehicle. In some cases, an approach includes: obtaining data indicating a location of the priority vehicle and a location of a destination for the priority vehicle; ranking each of a set of paths between the location of the priority vehicle and the location of the destination based upon a travel time for the priority vehicle along the set of paths; and sending instructions to vehicles on a highest-ranked path in the set of paths to initiate providing a right-of-way to the priority vehicle, wherein vehicles closer to the destination along the highest-ranked path are instructed to change a corresponding position prior to vehicles farther from the destination along the highest-ranked path.

    Thermoelectric cooling using through-silicon vias
    4.
    发明授权
    Thermoelectric cooling using through-silicon vias 有权

    公开(公告)号：US10043962B2

    公开(公告)日：2018-08-07

    申请号：US15147595

    申请日：2016-05-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sudeep Mandal ,  Richard S. Graf

    IPC: H01L35/30 ,  H01L35/32 ,  H01L35/10 ,  H01L23/38 ,  H01L35/34

    Abstract: Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via.

    INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION
    7.
    发明申请
    INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION 审中-公开
    集成电路时序可变性降低

    公开(公告)号：US20160117433A1

    公开(公告)日：2016-04-28

    申请号：US14525320

    申请日：2014-10-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric A. Foreman ,  Chaitanya Kompalli ,  Sudeep Mandal ,  Sebastian T. Ventrone

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/84

    Abstract: As disclosed herein, a method, executed by a computer, for integrated circuit timing variability reduction includes loading a netlist that corresponds to a chip design, where the chip design includes one or more circuits and a plurality of post-fill features, traversing a portion of the netlist corresponding to a circuit, determining a post-fill environment for the circuit from a plurality of post-fill features, and modeling a timing variance for the circuit based on the post-fill environment. The method may also include changing one or more post-fill features to achieve a targeted delay. The method may include generating a report of circuit timing and timing variances. One or more circuits can be concurrently traversed. The timing variance can be modeled with the use of a scaling factor for a standard timing variance. A computer system and computer program product corresponding to the method are also disclosed herein.

    Abstract translation: 如本文所公开的，由计算机执行的用于集成电路定时可变性降低的方法包括加载对应于芯片设计的网表，其中芯片设计包括一个或多个电路和多个后填充特征，遍历部分 所述网表对应于电路，从多个后填充特征确定所述电路的填充后环境，以及基于所述填充后环境对所述电路的定时方差进行建模。 该方法还可以包括改变一个或多个后填充特征以实现目标延迟。 该方法可以包括生成电路定时和定时方差的报告。 可以同时遍历一个或多个电路。 定时方差可以用标准时间方差的缩放因子来建模。 本文还公开了与该方法对应的计算机系统和计算机程序产品。

    PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) USING BACK-BIAS COMPENSATION
    9.
    发明申请
    PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) USING BACK-BIAS COMPENSATION 有权

    公开(公告)号：US20180082007A1

    公开(公告)日：2018-03-22

    申请号：US15270598

    申请日：2016-09-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sudeep Mandal ,  Jeanne P. Bickford

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.

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