公开(公告)号：US20160314826A1

公开(公告)日：2016-10-27

申请号：US14696050

申请日：2015-04-24

Applicant: INTEL CORPORATION

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  James W. TSCHANZ ,  Shih-Lien L. LU

IPC: G11C11/16

CPC classification number: G11C11/1659 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Abstract translation: 根据本公开的各种实施例，描述了诸如自旋传递转矩（STT）随机存取存储器（RAM），STTRAM的MRAM存储器中的杂散磁场减轻。 在一个实施例中，可以通过产生磁场来补偿可能导致存储器的位单元改变状态的杂散磁场来促进STTRAM中位单元位值存储状态的保持。 在另一个实施例中，可以通过选择性地暂停对一行存储器的访问来临时终止可能导致存储器的位单元改变状态的杂散磁场来促进STTRAM中位单元位值存储状态的保持。 本文描述了其它方面。

公开(公告)号：US20160232968A1

公开(公告)日：2016-08-11

申请号：US15025229

申请日：2013-12-05

Applicant: INTEL CORPORATION

Inventor： Nathaniel J. AUGUST ,  Pulkit JAIN ,  Stefan RUSU ,  Fatih HAMZAOGLU ,  Rangharajan VENKATESAN ,  Muhammad KHELLAH ,  Charles AUGUSTINE ,  Carlos TOKUNAGA ,  James W. TSCHANZ ,  Yih WANG

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Abstract translation: 描述了一种包括使用电阻性存储器保持的存储单元的装置。 该装置包括：存储元件，包括交叉耦合到第二反相器件的第一反相器件; 具有至少一个电阻性存储器元件的恢复电路，所述恢复电路耦合到所述第一反相器件的输出; 耦合到所述第一反相装置的输出的第三反相装置; 耦合到第三反相装置的输出的第四反相装置; 以及具有至少一个电阻性存储器元件的保存电路，所述保存电路耦合到所述第三反相器件的输出端。

公开(公告)号：US20170337958A1

公开(公告)日：2017-11-23

申请号：US15495936

申请日：2017-04-24

Applicant: INTEL CORPORATION

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  James W. TSCHANZ ,  Shih-Lien L. LU

IPC: G11C11/16

Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

公开(公告)号：US20170178710A1

公开(公告)日：2017-06-22

申请号：US15115461

申请日：2014-03-07

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Carlos TOKUNAGA ,  James W. TSCHANZ

IPC: G11C11/16 ,  H03M1/12

CPC classification number: G11C11/1695 ,  G06F21/34 ,  G06F21/73 ,  G06F21/79 ,  G09C1/00 ,  G11C7/16 ,  G11C7/24 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0045 ,  G11C2013/005 ,  H03M1/12 ,  H03M1/124 ,  H04L9/0866

Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

公开(公告)号：US20170178708A1

公开(公告)日：2017-06-22

申请号：US15371122

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Wei WU ,  Shih-Lien LU ,  James W. TSCHANZ ,  Georgios PANAGOPOULOS ,  Helia NAEIMI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

公开(公告)号：US20170126249A1

公开(公告)日：2017-05-04

申请号：US14929163

申请日：2015-10-30

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Shih-lien L. LU ,  James W. TSCHANZ

IPC: H03M13/05 ,  H03M13/00

CPC classification number: H03M13/05 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/353 ,  H03M13/611 ,  H03M13/6502 ,  H03M13/6516

Abstract: In one embodiment, temperature dependent, multiple mode error correction in accordance with one aspect of this disclosure, is employed for a memory circuit containing arrays of memory cells. In one embodiment, a temperature sensor coupled to an array is configured to provide an output signal which is a function of the temperature of the array of memory cells. Multiple mode error correction code (ECC) logic having an input coupled to an output of the temperature sensor, is configured to encode write data and decode read data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells. Other aspects are described herein.

公开(公告)号：US20160294281A1

公开(公告)日：2016-10-06

申请号：US15032981

申请日：2013-12-20

Applicant: INTEL CORPORATION

Inventor： Jaydeep P. KULKARNI ,  Pascal A. MEINERZHAGEN ,  Dinesh SOMASEKHAR ,  James W. TSCHANZ ,  Vivek K. DE

IPC: H02M3/07 ,  H03K19/21 ,  G06F3/041 ,  H03K3/037

CPC classification number: H02M3/073 ,  G06F3/041 ,  H02J7/00 ,  H03K3/0377 ,  H03K19/21

Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

Abstract translation: 描述了一种用于电源管理的装置。 该装置包括：第一电源节点; 第二电源节点; 耦合到所述第一电源节点和所述第二电源节点的可控设备，所述可控设备可操作以将所述第一电源节点缩短到所述第二电源节点; 耦合到所述第二电源节点的负载; 以及耦合到第一和第二电源节点的电荷恢复泵（CRP）。

公开(公告)号：US20160156355A1

公开(公告)日：2016-06-02

申请号：US15016260

申请日：2016-02-04

Applicant: Intel Corporation

Inventor： Arijit RAYCHOWDHURY ,  James W. TSCHANZ ,  Vivek DE

IPC: H03K19/177 ,  G11C11/16

CPC classification number: H03K19/17728 ,  G11C11/16 ,  H03K19/177

Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

Abstract translation: 这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。 基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。