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公开(公告)号：US09865581B2
公开(公告)日：2018-01-09
申请号：US14940621
申请日：2015-11-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joo-Hee Jang , Pil-Kyu Kang , Seok-Ho Kim , Tae-Yeong Kim , Hyo-Ju Kim , Byung-Lyul Park , Jum-Yong Park , Jin-Ho An , Kyu-Ha Lee , Yi-Koan Hong
IPC: H01L25/00 , H01L23/532 , H01L21/768 , H01L27/146
CPC classification number: H01L25/50 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14634 , H01L27/14636 , H01L27/14643 , H01L27/1469 , H01L2224/0508 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05547 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/08121 , H01L2924/0002 , H01L2924/00 , H01L2924/04941 , H01L2924/04953
Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.
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公开(公告)号：US20170062308A1
公开(公告)日：2017-03-02
申请号：US15151079
申请日：2016-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ju-ll Choi , Hyo-Ju Kim , Yeun-Sang Park , Atsushi Fujisaki , Kwang-Jin Moon , Byung-Lyul Park
IPC: H01L23/48 , H01L23/532 , H01L23/00 , H01L23/528 , H01L23/522 , H01L23/31 , H01L23/29
CPC classification number: H01L23/481 , H01L21/486 , H01L21/76807 , H01L21/76898 , H01L23/291 , H01L23/3171 , H01L23/3192 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/17 , H01L2224/03002 , H01L2224/0401 , H01L2224/05017 , H01L2224/05018 , H01L2224/05019 , H01L2224/05025 , H01L2224/05027 , H01L2224/05082 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05547 , H01L2224/05568 , H01L2224/05571 , H01L2224/05644 , H01L2224/06181 , H01L2224/13006 , H01L2224/131 , H01L2224/13139 , H01L2224/13147 , H01L2224/16146 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2924/01013 , H01L2924/01029 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/0501 , H01L2924/05032 , H01L2924/05042 , H01L2924/05442 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10328 , H01L2924/10329 , H01L2924/10331 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/00014 , H01L2924/00012 , H01L2924/014
Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.
Abstract translation: 一种半导体器件包括穿透衬底的通孔结构，所述通孔结构的一部分在所述衬底的表面上暴露，所述保护层图案结构设置在所述衬底的表面上并且包括第一保护层图案和第二保护 所述第一保护层图案围绕所述通孔结构的所述暴露部分的下侧壁并暴露所述通孔结构的所述暴露部分的上侧壁，所述第二保护层图案暴露所述第一保护的顶表面的一部分 所述衬垫结构设置在所述通孔结构和所述保护层图案结构上并且覆盖由所述第二保护层图案暴露的所述第一保护层图案的顶表面。
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公开(公告)号：US09728490B2
公开(公告)日：2017-08-08
申请号：US15151079
申请日：2016-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ju-Il Choi , Hyo-Ju Kim , Yeun-Sang Park , Atsushi Fujisaki , Kwang-Jin Moon , Byung-Lyul Park
IPC: H01L23/485 , H01L23/48 , H01L23/31 , H01L23/532 , H01L23/29 , H01L23/528 , H01L23/522 , H01L23/00 , H01L21/768 , H01L23/498 , H01L21/48
CPC classification number: H01L23/481 , H01L21/486 , H01L21/76807 , H01L21/76898 , H01L23/291 , H01L23/3171 , H01L23/3192 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/17 , H01L2224/03002 , H01L2224/0401 , H01L2224/05017 , H01L2224/05018 , H01L2224/05019 , H01L2224/05025 , H01L2224/05027 , H01L2224/05082 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05547 , H01L2224/05568 , H01L2224/05571 , H01L2224/05644 , H01L2224/06181 , H01L2224/13006 , H01L2224/131 , H01L2224/13139 , H01L2224/13147 , H01L2224/16146 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2924/01013 , H01L2924/01029 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/0501 , H01L2924/05032 , H01L2924/05042 , H01L2924/05442 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10328 , H01L2924/10329 , H01L2924/10331 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/00014 , H01L2924/00012 , H01L2924/014
Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.
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Patent Agency Ranking
公开(公告)号：US09520361B2
公开(公告)日：2016-12-13
申请号：US14937406
申请日：2015-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Pil-Kyu Kang , Seok-Ho Kim , Tae-Yeong Kim , Hyo-Ju Kim , Byung-Lyul Park , Joo-Hee Jang , Jin-Ho Chun
IPC: H01L23/532 , H01L25/065
CPC classification number: H01L23/53228 , H01L21/76843 , H01L23/53209 , H01L23/53214 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L25/0657 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14629 , H01L27/14632 , H01L27/14634 , H01L27/14636 , H01L27/1469 , H01L2224/08121 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.
Abstract translation: 提供半导体器件。 半导体器件包括衬底，衬底上的第一导电结构和第一导电结构上的第二导电结构。 半导体器件包括在第一和第二导电结构的相应侧壁上的第一和第二金属扩散阻挡层。 半导体器件包括在第一和第二金属扩散阻挡层之间的绝缘层。 此外，半导体器件在绝缘层中包括金属扩散屏蔽图案并且与第一导电结构间隔开。
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公开(公告)号：US20160141249A1
公开(公告)日：2016-05-19
申请号：US14937406
申请日：2015-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Pil-Kyu Kang , Seok-Ho Kim , Tae-Yeong Kim , Hyo-Ju Kim , Byung-Lyul Park , Joo-Hee Jang , Jin-Ho Chun
IPC: H01L23/532 , H01L25/065
CPC classification number: H01L23/53228 , H01L21/76843 , H01L23/53209 , H01L23/53214 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L25/0657 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14629 , H01L27/14632 , H01L27/14634 , H01L27/14636 , H01L27/1469 , H01L2224/08121 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.
Abstract translation: 提供半导体器件。 半导体器件包括衬底，衬底上的第一导电结构和第一导电结构上的第二导电结构。 半导体器件包括在第一和第二导电结构的相应侧壁上的第一和第二金属扩散阻挡层。 半导体器件包括在第一和第二金属扩散阻挡层之间的绝缘层。 此外，半导体器件在绝缘层中包括金属扩散屏蔽图案并且与第一导电结构间隔开。
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公开(公告)号：US20160141282A1
公开(公告)日：2016-05-19
申请号：US14940621
申请日：2015-11-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joo-Hee Jang , Pil-Kyu Kang , Seok-Ho Kim , Tae-Yeong Kim , Hyo-Ju Kim , Byung-Lyul Park , Jum-Yong Park , Jin-Ho An , Kyu-Ha Lee , Yi-Koan Hong
IPC: H01L25/00 , H01L21/321
CPC classification number: H01L25/50 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14634 , H01L27/14636 , H01L27/14643 , H01L27/1469 , H01L2224/0508 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05547 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/08121 , H01L2924/0002 , H01L2924/00 , H01L2924/04941 , H01L2924/04953
Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.
Abstract translation: 在基板上形成第一绝缘层。 在第一绝缘层中形成开口。 阻挡层形成在第一绝缘层上并与开口中的第一绝缘层的侧壁一致，并且在阻挡层上形成导电层。 执行化学机械抛光以露出第一绝缘层并在开口中留下阻挡层图案，并且在开口中的阻挡层图案上具有导电层图案，其中导电层图案的一部分突出于绝缘体的上表面上方 层和阻挡层图案的上表面。 在第一绝缘层，阻挡层图案和导电层图案上形成第二绝缘层，并平坦化以暴露导电层图案。 第二衬底可以结合到暴露的导电层图案。
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公开(公告)号：US09287251B2
公开(公告)日：2016-03-15
申请号：US14794561
申请日：2015-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Pil-Kyu Kang , Seok-Ho Kim , Tae-Yeong Kim , Hyo-Ju Kim , Byung-Lyul Park , Yeun-Sang Park , Jin-Ho An , Ho-Jin Lee , Joo-Hee Jang , Deok-Young Jung
IPC: H01L21/00 , H01L25/00 , H01L21/768 , H01L23/00
CPC classification number: H01L25/50 , H01L21/76831 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/03462 , H01L2224/03616 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05166 , H01L2224/05176 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05547 , H01L2224/05571 , H01L2224/05647 , H01L2224/08121 , H01L2224/08147 , H01L2224/80013 , H01L2224/80895 , H01L2224/80896 , H01L2924/00014 , H01L2924/049 , H01L2924/04953 , H01L2924/04941 , H01L2924/00012
Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate. A plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.
Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构。 在其上分别具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺。 第一和第二导电图案结构彼此接触以接合第一和第二基板。
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公开(公告)号：US20160020197A1
公开(公告)日：2016-01-21
申请号：US14794561
申请日：2015-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Pil-Kyu Kang , Seok-Ho Kim , Tae-Yeong Kim , Hyo-Ju Kim , Byung-Lyul Park , Yeun-Sang Park , Jin-Ho An , Ho-Jin Lee , Joo-Hee Jang , Deok-Young Jung
IPC: H01L25/00 , H01L23/00 , H01L21/768
CPC classification number: H01L25/50 , H01L21/76831 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/03462 , H01L2224/03616 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05166 , H01L2224/05176 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05547 , H01L2224/05571 , H01L2224/05647 , H01L2224/08121 , H01L2224/08147 , H01L2224/80013 , H01L2224/80895 , H01L2224/80896 , H01L2924/00014 , H01L2924/049 , H01L2924/04953 , H01L2924/04941 , H01L2924/00012
Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate, plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.
Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构，在其上具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺， ， 分别。 第一和第二导电图案结构彼此接触以接合第一和第二基板。
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