公开(公告)号：US20160064328A1

公开(公告)日：2016-03-03

申请号：US14469500

申请日：2014-08-26

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L23/538 ,  H01L25/07 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5383 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012

Abstract: Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.

Abstract translation: 实例通常提供堆叠的硅互连产品和制造方法。 堆叠的硅互连产品包括包含多个金属化层的无硅衬底中介层，其中至少一个金属化层包括由电介质材料隔开的多个金属段。 堆叠的硅互连产品还包括经由第一多个微胶片耦合到无硅衬底的插入件的第一侧的第一裸片。 堆叠的硅互连产品还包括第二裸片，其经由第二多个微胶片耦合到无硅衬底的中介层的第二侧，第二裸片通过多个金属化层的金属化层通信地耦合到第一裸片。

公开(公告)号：US09006030B1

公开(公告)日：2015-04-14

申请号：US14100678

申请日：2013-12-09

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam ,  Paul Y. Wu ,  Manoj Nachnani

IPC: H01L23/492 ,  H01L21/58 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: An integrated circuit includes a stacked conductive layer interposer and a first die at least partially encapsulated in a mold material. The first die is mechanically and electrically attached to a top surface of the stacked conductive layer interposer using solder bumps. The integrated circuit further includes a first warpage correction layer.

Abstract translation: 集成电路包括层叠的导电层插入件和至少部分地封装在模具材料中的第一模具。 使用焊料凸块将第一裸片机械和电连接到堆叠的导电层插入件的顶表面。 集成电路还包括第一翘曲校正层。

公开(公告)号：US20140252599A1

公开(公告)日：2014-09-11

申请号：US13791819

申请日：2013-03-08

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam ,  Namhoon Kim ,  Joong-Ho Kim

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76802 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/28 ,  H05K3/4682

Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.

Abstract translation: 一种用于层叠硅互连技术（SSIT）产品的无衬底插入件包括：多个金属化层，至少最底层的金属化层包括多个金属段，其中多个金属段中的每一个均为 形成在金属化层的最底层的顶表面和底表面之间，并且金属段由最底层中的电介质材料分离; 以及形成在最底层的底表面上的电介质层，其中介电层包括用于提供与最底层中的多个金属段接触的一个或多个开口。

公开(公告)号：US09147661B1

公开(公告)日：2015-09-29

申请号：US14171517

申请日：2014-02-03

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13025 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92135 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00015 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2224/32507 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2224/1147 ,  H01L2224/034 ,  H01L2224/11849

Abstract: Implementations described herein generally relate to chip packaging, and in particular, to solder bump structures for a semiconductor device and methods of fabricating the same. In one implementation, a solder bump assembly is provided. The solder bump assembly comprises a conductive bond pad formed on a substrate. A conductive pillar is formed on the conductive bond pad. A plating layer is formed on the conductive pillar, wherein the plating layer comprises copper and nickel. A solder bump is formed on the plating layer in electrical communication with the plating layer. The plating layer may be a bi-layer structure comprising a nickel layer formed on the conductive pillar and a copper layer formed on the nickel layer in electrical communication with the solder bump. The plating layer may be a copper-nickel alloy.

Abstract translation: 本文描述的实施方式通常涉及芯片封装，特别涉及用于半导体器件的焊料凸块结构及其制造方法。 在一个实施方案中，提供了焊料凸块组件。 焊料凸块组件包括形成在衬底上的导电接合焊盘。 在导电接合焊盘上形成导电柱。 在导电柱上形成镀层，其中镀层包括铜和镍。 在镀层上形成与镀层电连通的焊料凸块。 镀层可以是包括形成在导电柱上的镍层和形成在镍层上与焊料凸块电连通的铜层的双层结构。 镀层可以是铜镍合金。

公开(公告)号：US09418966B1

公开(公告)日：2016-08-16

申请号：US14665908

申请日：2015-03-23

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/535 ,  H01L23/528 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/01 ,  H01L24/11 ,  H01L24/81 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/16145 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: In one example, a semiconductor assembly comprises a first IC die, a second IC die, and a bridge module. The first IC die includes, on a top side thereof, first interconnects of a plurality of interconnects and first inter-die contacts of a plurality of inter-die contacts. The second IC die includes, on a top side thereof, second interconnects of the plurality of interconnects and second inter-die contacts of the plurality of inter-die contracts. The bridge module is disposed between the first interconnects and the second interconnects and includes bridge interconnects on a top side thereof, the bridge interconnects mechanically and electrically coupled to the plurality of inter-die contacts, and layer(s) of conductive interconnect disposed on the top side thereof to route signals between the first IC and the second IC. A back side of the bridge module does not extend beyond a height of the plurality of interconnects.

Abstract translation: 在一个示例中，半导体组件包括第一IC管芯，第二IC管芯和桥接模块。 第一IC芯片在其顶侧上包括多个互连的第一互连和多个晶片间接触的第一晶片间接触。 第二IC管芯在其顶侧上包括多个互连件中的第二互连和多个管芯间合同的第二管芯间接触。 桥模块设置在第一互连和第二互连之间，并且在其顶侧上包括桥互连，桥互连机械地和电耦合到多个管芯间接触，以及设置在第二互连层上的导电互连层 其顶侧以在第一IC和第二IC之间路由信号。 桥模块的背面不延伸超出多个互连的高度。

公开(公告)号：US20140262440A1

公开(公告)日：2014-09-18

申请号：US13827048

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Namhoon Kim ,  Joong-Ho Kim ,  Suresh Ramalingam ,  Paul Y. Wu ,  Woon-Seong Kwon ,  Dennis C.P. Leung

IPC: H05K1/02

CPC classification number: H05K1/02 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/16225

Abstract: A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer.

Abstract translation: 多层核心有机封装基板包括：包含至少两个有机芯层的多层芯，其中所述至少两个有机芯层中的两个被芯金属层分隔开; 形成在所述多芯层的顶部上的第一多个堆积层; 以及形成在所述多芯层下方的第二多个积聚层。

公开(公告)号：US10468351B2

公开(公告)日：2019-11-05

申请号：US14469500

申请日：2014-08-26

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/07 ,  H01L23/16 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31

Abstract: Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.

公开(公告)号：US09831104B1

公开(公告)日：2017-11-28

申请号：US14935011

申请日：2015-11-06

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/67126 ,  H01L23/3142 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: Techniques for providing a unified underfill and encapsulation for integrated circuit die assemblies. These techniques include a molding technique that includes dipping a die assembly including a substrate and one or more dies into a chamber having molding material, sealing the chamber, and lowering pressure in the chamber to coax the molding material into space between the die(s) and substrate. The use of this molding technique, as contrasted with a capillary underfill technique in which underfill material is laid down adjacent dies and fills space under the die via capillary action, provides several benefits. One benefit is that the molding material can include a higher silica particle filler content (% by weight) than the material for the capillary underfill technique, which improves CTE. Another benefit is that various design constraints related to, for example, warpage and partial underfill are eliminated or improved.

公开(公告)号：US09627329B1

公开(公告)日：2017-04-18

申请号：US14175920

申请日：2014-02-07

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2224/73204

Abstract: A TSV interposer having a reinforced edge and methods for fabricating an IC package utilizing the same are provided. In one embodiment, a chip package includes an interposer having a wiring layer and a die disposed on a surface of the interposer. The die is electrically connected to the wiring layer of the interposer. A die underfill material is disposed between the interposer and the die. The die underfill material at least partially covers a side of the die that extends away from the surface of the interposer. Stiffening material is disposed in contact with the interposer and the die underfill material.

公开(公告)号：US09245865B1

公开(公告)日：2016-01-26

申请号：US14571173

申请日：2014-12-15

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L31/12 ,  H01L21/50 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/3142 ,  H01L21/563 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0655 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14179 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83365 ,  H01L2224/8385 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K1/0271 ,  H05K1/141 ,  H05K1/144 ,  H05K3/28 ,  H05K3/3436 ,  H05K2201/09036 ,  H05K2201/2072 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/05442

Abstract: In an example, an integrated circuit (IC) package includes a package substrate, an IC die, solder bumps, a first plurality of trenches, and underfill material. The IC die includes a front surface and a back surface, the front surface facing the package substrate and including a conductive interface. The solder bumps couple the conductive interface to the package substrate. The first plurality of trenches includes at least one trench proximate each corner of the IC die formed in the front surface of the IC die in an area between the conductive interface and a perimeter of the IC die. The underfill material is disposed between the front surface of the IC die and the package substrate, the underfill material being in contact with the first plurality of trenches.

Abstract translation: 在一个示例中，集成电路（IC）封装包括封装基板，IC管芯，焊料凸块，第一多个沟槽和底部填充材料。 IC芯片包括前表面和后表面，前表面面向封装衬底并且包括导电界面。 焊料凸块将导电界面耦合到封装衬底。 所述第一多个沟槽包括在所述IC芯片的前表面中形成于所述IC裸片的所述导电界面和所述IC芯片的周边之间的区域中的靠近所述IC管芯的每个拐角的至少一个沟槽。 底部填充材料设置在IC管芯的前表面和封装衬底之间，底部填充材料与第一多个沟槽接触。