公开(公告)号：US20040112442A1

公开(公告)日：2004-06-17

申请号：US10670997

申请日：2003-09-24

Applicant: California Institute of Technology

Inventor： Sebastian J. Maerkl ,  Todd A. Thorsen ,  Xiaoyan Bao ,  Stephen R. Quake ,  Vincent Studer

IPC: F16K011/20

CPC classification number: C12Q1/28 ,  B01L3/5025 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0861 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0655 ,  B81B2201/0214 ,  B81B2201/054 ,  B81B2201/07 ,  B81C1/00119 ,  F15C5/00 ,  F16K11/20 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0059 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0078 ,  F16K2099/008 ,  F16K2099/0084 ,  F16K2099/0094 ,  Y10T137/0318 ,  Y10T137/0329 ,  Y10T137/2224 ,  Y10T137/85938 ,  Y10T137/87249

Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.

Abstract translation: 高密度微流控芯片包含具有数千个微机械阀门和数百个单独可寻址腔室的管道网络。 这些流体装置类似于使用大规模集成（LSI）制造的电子集成电路。 这些网络的一个组件是流体多路复用器，它是二进制阀模式的组合阵列，通过允许使用最少数量的输入的复杂流体操纵来指数地增加网络的处理能力。 这些集成的微流体网络可用于构建各种高度复杂的微流体装置，例如比较器阵列的微流体模拟装置和类似于电子随机存取存储器的微流体存储器存储装置。

公开(公告)号：US5717631A

公开(公告)日：1998-02-10

申请号：US507676

申请日：1995-07-25

Applicant: L. Richard Carley ,  Michael L. Reed ,  Gary K. Fedder ,  Suresh Santhanam

Inventor： L. Richard Carley ,  Michael L. Reed ,  Gary K. Fedder ,  Suresh Santhanam

IPC: G01B21/30 ,  B62D57/00 ,  B81B3/00 ,  B81B5/00 ,  B81B7/02 ,  B81C3/00 ,  G01N13/10 ,  G01N37/00 ,  G11B5/00 ,  G11B9/00 ,  G11B9/14 ,  H02N1/00 ,  H01L21/44

CPC classification number: H02N1/006 ,  B81C1/0015 ,  B82Y10/00 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/1445 ,  B81B2201/07 ,  B81B2201/12 ,  B81B2203/0361 ,  B81C2201/0109 ,  B81C2201/0132 ,  G11B2005/0002 ,  Y10S977/861 ,  Y10S977/881 ,  Y10S977/888 ,  Y10S977/89

Abstract: A microelectromechanical device is comprised of a cantilevered beam positioned above, and free to move relative to, a substrate. The beam may carry a plurality of conductors which are insulated from one another. One or more tips is positioned on the beam with each tip being in electrical contact with one of the conductors. A memory device may be constructed by providing an array of such cantilevered beams proximate to a layer of media. Devices for positioning the beam in x and y directions perpendicular to each other and parallel to the layer of media and in a z direction perpendicular to the media are provided. A control circuit generates control signals input to the positioning devices for positioning the tips according to x, y, and z coordinates. A read/write circuit which is in electrical communication with the conductors of the beam, provide signals to the tips to cause the tips to write those signals to the layer of media in a write mode and to read previously written signals sensed by the tips in a read mode. A fabrication method is also disclosed.

Abstract translation: 微机电装置包括位于上方并相对于衬底自由移动的悬臂梁。 梁可以承载彼此绝缘的多个导体。 一个或多个尖端位于梁上，每个尖端与导体之一电接触。 可以通过提供靠近一层介质的这种悬臂梁的阵列来构造存储器件。 提供了用于将光束定位在彼此垂直并且平行于介质层并且垂直于介质的z方向上的x和y方向上的装置。 控制电路产生输入到定位装置的控制信号，用于根据x，y和z坐标定位尖端。 与光束的导体电连通的读/写电路向尖端提供信号，以使尖端以写模式将这些信号写入介质层，并读取由尖端感测的先前写入的信号 读取模式。 还公开了一种制造方法。

公开(公告)号：US11908512B2

公开(公告)日：2024-02-20

申请号：US18148684

申请日：2022-12-30

Applicant: Micron Technology, Inc.

Inventor： Tomoharu Tanaka ,  Yoshiaki Fukuzumi

IPC: G11C11/4097 ,  G11C11/4091 ,  B81B7/00 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: G11C11/4097 ,  B81B7/008 ,  G11C11/4091 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  B81B2201/07

Abstract: A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20140065653A1

公开(公告)日：2014-03-06

申请号：US13679328

申请日：2012-11-16

Applicant: California Institute of Technology

Inventor： Sebastian J. Maerkl ,  Todd A. Thorsen ,  Xiaoyan Bao ,  Stephen R. Quake ,  Vincent Studer

IPC: C12Q1/28

CPC classification number: C12Q1/28 ,  B01L3/5025 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0861 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0655 ,  B81B2201/0214 ,  B81B2201/054 ,  B81B2201/07 ,  B81C1/00119 ,  F15C5/00 ,  F16K11/20 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0059 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0078 ,  F16K2099/008 ,  F16K2099/0084 ,  F16K2099/0094 ,  Y10T137/0318 ,  Y10T137/0329 ,  Y10T137/2224 ,  Y10T137/85938 ,  Y10T137/87249

Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.

Abstract translation: 高密度微流控芯片包含具有数千个微机械阀门和数百个单独可寻址腔室的管道网络。 这些流体装置类似于使用大规模集成（LSI）制造的电子集成电路。 这些网络的一个组件是流体多路复用器，它是二进制阀模式的组合阵列，通过允许使用最少数量的输入的复杂流体操纵来指数地增加网络的处理能力。 这些集成的微流体网络可用于构建各种高度复杂的微流体装置，例如比较器阵列的微流体模拟装置和类似于电子随机存取存储器的微流体存储器存储装置。

公开(公告)号：US07687297B2

公开(公告)日：2010-03-30

申请号：US11824465

申请日：2007-06-29

Applicant: John Heck ,  Tsung-Kuan Allen Chou

Inventor： John Heck ,  Tsung-Kuan Allen Chou

IPC: H01L21/00

CPC classification number: B81C1/00246 ,  B81B2201/07 ,  B81B2201/11 ,  B81B2201/12 ,  B81B2203/0118 ,  B81C2203/0735 ,  B82Y10/00 ,  G11B9/1436

Abstract: In one embodiment, the present invention includes a method for forming a sacrificial oxide layer on a base layer of a microelectromechanical systems (MEMS) probe, patterning the sacrificial oxide layer to provide a first trench pattern having a substantially rectangular form and a second trench pattern having a substantially rectangular portion and a lateral portion extending from the substantially rectangular portion, and depositing a conductive layer on the patterned sacrificial oxide layer to fill the first and second trench patterns to form a support structure for the MEMS probe and a cantilever portion of the MEMS probe. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括在微机电系统（MEMS）探针的基底层上形成牺牲氧化物层的方法，图案化牺牲氧化物层以提供具有基本矩形形状的第一沟槽图案和第二沟槽图案 具有基本上矩形的部分和从所述大致矩形部分延伸的横向部分，以及在所述图案化的牺牲氧化物层上沉积导电层以填充所述第一和第二沟槽图案以形成用于所述MEMS探针的支撑结构， MEMS探针。 描述和要求保护其他实施例。

公开(公告)号：US07494593B1

公开(公告)日：2009-02-24

申请号：US10879971

申请日：2004-06-28

Applicant: Chien-Hua Chen ,  John Chen ,  Sriram Ramamoorthi

Inventor： Chien-Hua Chen ,  John Chen ,  Sriram Ramamoorthi

IPC: C25F3/12

CPC classification number: B81C1/0015 ,  B81B2201/07

Abstract: A method is disclosed for forming a single crystal cantilever and tip on a substrate. The method can include the operation of defining an implant area on the substrate with a layer of photoresist. A further operation can be implanting oxygen into the substrate in the implant area to a predetermined depth to form a buried oxide layer. The buried oxide layer can define a bottom of the single crystal cantilever and tip. Another operation can involve shaping the single crystal cantilever and tip from the substrate above the buried oxide layer.

Abstract translation: 公开了一种用于在基板上形成单晶悬臂和尖端的方法。 该方法可以包括在衬底上用光致抗蚀剂层限定植入区域的操作。 进一步的操作可以是将植入区域中的氧注入到预定深度的衬底中以形成掩埋氧化物层。 掩埋氧化物层可以限定单晶悬臂和尖端的底部。 另外的操作可以包括从掩埋氧化物层上方的衬底上形成单晶悬臂和尖端。

公开(公告)号：US20230143421A1

公开(公告)日：2023-05-11

申请号：US18148684

申请日：2022-12-30

Applicant: Micron Technology, Inc .

Inventor： Tomoharu Tanaka ,  Yoshiaki Fukuzumi

IPC: G11C11/4097 ,  H10B41/20 ,  H10B41/41 ,  H10B43/40 ,  G11C11/4091 ,  B81B7/00 ,  H10B43/20

CPC classification number: G11C11/4097 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11573 ,  G11C11/4091 ,  B81B7/008 ,  H01L27/11578 ,  B81B2201/07

Abstract: A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US09755041B2

公开(公告)日：2017-09-05

申请号：US14701502

申请日：2015-04-30

Applicant: Purdue Research Foundation

Inventor： Muhammad Ashraful Alam ,  Muhammad Masuduzzaman ,  Ankit Jain

IPC: G01L9/00 ,  H01L21/00 ,  H01L29/51 ,  H01L29/78 ,  H01L27/11502 ,  H01L27/11585 ,  B81B7/02 ,  H01G4/38 ,  H01L27/08 ,  H01G5/16 ,  H01G5/40 ,  H01G7/06 ,  H01L49/02

CPC classification number: H01L29/515 ,  B81B7/02 ,  B81B2201/014 ,  B81B2201/016 ,  B81B2201/07 ,  H01G4/38 ,  H01G5/16 ,  H01G5/40 ,  H01G7/06 ,  H01L27/0805 ,  H01L27/11502 ,  H01L27/11585 ,  H01L29/516 ,  H01L29/7842

Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.

公开(公告)号：US09714443B2

公开(公告)日：2017-07-25

申请号：US13679328

申请日：2012-11-16

Applicant: California Institute of Technology

Inventor： Sebastian J. Maerkl ,  Todd A. Thorsen ,  Xiaoyan Bao ,  Stephen R. Quake ,  Vincent Studer

IPC: B81B3/00 ,  B81B7/00 ,  B01L3/00 ,  C12Q1/28 ,  B81C1/00 ,  F15C5/00 ,  F16K99/00

CPC classification number: C12Q1/28 ,  B01L3/5025 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0861 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0655 ,  B81B2201/0214 ,  B81B2201/054 ,  B81B2201/07 ,  B81C1/00119 ,  F15C5/00 ,  F16K11/20 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0059 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0078 ,  F16K2099/008 ,  F16K2099/0084 ,  F16K2099/0094 ,  Y10T137/0318 ,  Y10T137/0329 ,  Y10T137/2224 ,  Y10T137/85938 ,  Y10T137/87249

Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.

公开(公告)号：US20160332871A1

公开(公告)日：2016-11-17

申请号：US15220267

申请日：2016-07-26

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Giuseppe Barillaro ,  Alessandro Diligenti ,  Caterina Riva ,  Roberto Campedelli ,  Stefano Losa

IPC: B81C1/00

CPC classification number: B81C1/00539 ,  B81B2201/038 ,  B81B2201/07 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/019 ,  B81C1/00595 ,  B81C2201/0136 ,  B81C2203/0714 ,  H01L27/10

Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity and a top surface; forming a first interaction region having a second type of conductivity, opposite to the first type of conductivity, in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity, so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.

Abstract translation: 一种用于制造用于存储介质的微机电类型的相互作用系统的方法，具有支撑元件的相互作用系统和由支撑元件承载的相互作用元件，其设想是提供具有基板的半导体材料晶片，其具有 第一类导电性和顶面; 在所述顶表面附近的所述衬底的表面部分中形成具有与所述第一类型导电性相反的第二导电类型的第一相互作用区域; 并且从顶表面开始进行基板的电化学蚀刻，蚀刻相对于第二类型的导电性是选择性的，以便去除基板的表面部分并将第一相互作用区域与基板分离，从而形成 支撑元件。