公开(公告)号：US20170302381A1

公开(公告)日：2017-10-19

申请号：US15640032

申请日：2017-06-30

Applicant: INPHI CORPORATION

Inventor： Jamal RIANI ,  Sudeep BHOJA

IPC: H04B10/27 ,  H04L27/06 ,  H04B14/00 ,  H03K9/02 ,  H04B10/61 ,  H04B10/25 ,  H04L27/34 ,  H04L27/02

CPC classification number: H04B10/27 ,  H03K9/02 ,  H04B10/2504 ,  H04B10/61 ,  H04B14/004 ,  H04L27/02 ,  H04L27/06 ,  H04L27/34

Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using nDSQ format(s) over optical communication networks. In certain embodiments, the communication interface is used by various devices, such as spine switches and leaf switches, within a spine-leaf network architecture, which allows large amount of data to be shared among servers.

公开(公告)号：US09793863B2

公开(公告)日：2017-10-17

申请号：US14987673

申请日：2016-01-04

Applicant: INPHI CORPORATION

Inventor： Rahul Shringarpure ,  Tom Peter Edward Broekaert ,  Gaurav Mahajan

IPC: H04B10/61 ,  H03F3/08 ,  H03F3/45 ,  H03F1/02 ,  H04B10/69

CPC classification number: H03F3/082 ,  H03F1/0205 ,  H03F3/087 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/555 ,  H04B10/616 ,  H04B10/693

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

公开(公告)号：US20170285267A1

公开(公告)日：2017-10-05

申请号：US15088862

申请日：2016-04-01

Applicant: INPHI CORPORATION

Inventor： Masaki KATO ,  Radhakrishnan L. NAGARAJAN

IPC: G02B6/27 ,  G02B6/293 ,  G02B6/122 ,  G02B6/28

CPC classification number: G02B6/274 ,  G02B6/1228 ,  G02B6/29352 ,  G02B6/29395

Abstract: An apparatus of polarization self-compensated delay line interferometer. The apparatus includes a first waveguide arm of a first material of a first length disposed between an input coupler and an output coupler and a second waveguide arm of the first material of a second length different from the first length disposed between the same input coupler and the same output coupler. The apparatus produces an interference spectrum with multiple periodic passband peaks where certain TE (transverse electric) and TM (transverse magnetic) polarization mode passband peaks are lined up. The apparatus further includes a section of waveguide of a birefringence material of a third length added to the second waveguide arm to induce a phase shift of the lined-up TE/TM passband peaks to a designated grid as corresponding polarization compensated channels of a wide optical band.

公开(公告)号：US20170261708A1

公开(公告)日：2017-09-14

申请号：US15481994

申请日：2017-04-07

Applicant: INPHI CORPORATION

Inventor： Liang DING ,  Radhakrishnan L. NAGARAJAN ,  Roberto COCCIOLI

IPC: G02B6/42 ,  H04B10/40

CPC classification number: G02B6/4246 ,  G02B6/4214 ,  G02B6/4232 ,  G02B6/4245 ,  G02B6/4274 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12142 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/81 ,  H01L25/167 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/81191 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H04B10/40 ,  H05K1/0274 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2201/10378 ,  H05K2203/049 ,  Y02P70/611 ,  Y02P70/613

Abstract: A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.

公开(公告)号：US20170254968A1

公开(公告)日：2017-09-07

申请号：US15061941

申请日：2016-03-04

Applicant: INPHI CORPORATION

Inventor： Liang DING ,  Radhakrishnan L. NAGARAJAN ,  Roberto COCCIOLI

IPC: G02B6/42 ,  G02B6/13 ,  H01L25/16 ,  H01L21/768 ,  H01L21/56 ,  G02B6/30 ,  H01L23/00

CPC classification number: G02B6/428 ,  G02B6/13 ,  G02B6/30 ,  G02B6/4232 ,  G02B6/424 ,  G02B6/4245 ,  G02B6/4283 ,  G02B6/4295 ,  G02B2006/12121 ,  G02B2006/12142 ,  H01L21/565 ,  H01L21/76877 ,  H01L24/11 ,  H01L24/81 ,  H01L25/167 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/06 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1205 ,  H01L2924/141 ,  H01L2924/1426 ,  H01L2924/1433

Abstract: An optical transceiver by hybrid multichip integration. The optical transceiver includes a PCB with a plurality of prefabricated surface bonding sites. A first chip includes a FOWLP package of multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer is disposed on the PCB by respectively bonding a plurality of conductor balls between the dielectric redistribution layer and the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) in the dielectric molding layer. The optical transceiver further includes a second chip configured as a Sipho die comprising photonics devices embedded in a SOI wafer substantially free from any electronics device process. The second chip is stacked over the first chip with multiple conductor bumps being bonded respectively to the soldering material in the multiple TMVs.

公开(公告)号：US09746906B2

公开(公告)日：2017-08-29

申请号：US14791100

申请日：2015-07-02

Applicant: INPHI CORPORATION

Inventor： Fredrik Olsson ,  Shawn Lawrence Scouten ,  Ryan Patrick Donohue

IPC: G06F1/32 ,  H04L12/12

CPC classification number: G06F1/3281 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3234 ,  G06F1/3278 ,  G06F1/3287 ,  G06F1/3293 ,  H04L12/12 ,  Y02D10/157 ,  Y02D10/171 ,  Y02D50/20 ,  Y02D50/40 ,  Y02D50/42

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

公开(公告)号：US09742594B2

公开(公告)日：2017-08-22

申请号：US15372051

申请日：2016-12-07

Applicant: INPHI CORPORATION

Inventor： Stephane Dallaire ,  Benjamin Smith

IPC: H04L7/033 ,  H04L25/03 ,  H04L7/027

CPC classification number: H04L25/03006 ,  H04L7/027 ,  H04L25/03057 ,  H04L25/03885

Abstract: Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.

公开(公告)号：US20170230140A1

公开(公告)日：2017-08-10

申请号：US15494366

申请日：2017-04-21

Applicant: Inphi Corporation

Inventor： Benjamin P. SMITH ,  Arash FARHOODFAR

IPC: H04L1/00 ,  H03M13/29 ,  H04B10/532 ,  H04B10/69 ,  H04B10/54 ,  H04B10/516

CPC classification number: H04L1/0044 ,  H03M13/2906 ,  H04B10/50 ,  H04B10/516 ,  H04B10/5161 ,  H04B10/532 ,  H04B10/541 ,  H04B10/697 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/006 ,  H04L1/0065

Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.

公开(公告)号：US20170214469A1

公开(公告)日：2017-07-27

申请号：US15481920

申请日：2017-04-07

Applicant: INPHI CORPORATION

Inventor： Radhakrishnan L. NAGARAJAN ,  Todd ROPE

IPC: H04B10/524 ,  G02F1/225 ,  G02F1/01 ,  H03M1/68

CPC classification number: H04B10/5161 ,  G02F1/0123 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2001/212 ,  H03M1/682 ,  H04B10/524 ,  H04B10/541

Abstract: A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.

公开(公告)号：US09696604B1

公开(公告)日：2017-07-04

申请号：US15261669

申请日：2016-09-09

Applicant: INPHI CORPORATION

Inventor： Jie Lin ,  Masaki Kato ,  Robb Johnson

IPC: G02F1/225 ,  G02B6/134 ,  G02B6/136 ,  G02F1/21 ,  G02B6/12

CPC classification number: G02F1/2257 ,  G02B6/134 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12142 ,  G02B2006/12173 ,  G02F2001/212

Abstract: A method of forming a waveguide for a self-aligned Mach-Zehnder-Interferometer. The method includes forming a waveguide on a substrate and providing a first mask with a first opening exposing a first width and a pair of second widths towards opposite sides of the first width. Additionally, the method includes doping a first dopant of a first concentration through the first opening into a first thickness of the waveguide to form a first semiconducting phase thereof. The method includes providing a second mask with a second opening exposing part of the waveguide and doping a second dopant of a second concentration through the second opening into the part of the waveguide to form a second semiconductor phase thereof sharing a boundary with the first semiconducting phase to form a PN junction across the boundary. The boundary is allowed to vary with a margin of tolerance within the first width.