公开(公告)号：US09647625B2

公开(公告)日：2017-05-09

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02 ,  H03H9/02 ,  H03H3/04 ,  H03H9/00 ,  H03H9/17 ,  G02F1/1337 ,  G01N29/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

公开(公告)号：US09641143B2

公开(公告)日：2017-05-02

申请号：US15192151

申请日：2016-06-24

Applicant: STMicroelectronics SA

Inventor： Laurent Chabert

IPC: H03F3/45 ,  H04B1/06 ,  H03F1/02 ,  H03F3/19 ,  H03F3/193 ,  H03F3/30 ,  H03D7/14 ,  G01S7/03

CPC classification number: H03F3/45282 ,  G01S7/03 ,  H03D7/1433 ,  H03D7/1458 ,  H03F1/0205 ,  H03F1/0261 ,  H03F3/19 ,  H03F3/193 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45372 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/91 ,  H03F2203/30015 ,  H03F2203/45081 ,  H03F2203/45112 ,  H03F2203/45154 ,  H03F2203/45288 ,  H04B1/06

Abstract: An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage.

公开(公告)号：US09615443B2

公开(公告)日：2017-04-04

申请号：US14487758

申请日：2014-09-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Stephane Monfray ,  Sandrine Lhostis ,  Christophe Maitre ,  Olga Kokshagina ,  Philippe Coronel

IPC: F28F27/00 ,  H05K1/02 ,  F28D9/00 ,  F28F27/02 ,  H01L23/473

CPC classification number: H05K1/0203 ,  F28D9/0062 ,  F28F27/02 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip cooling device includes a network of micropipes. A first pipe portion and a second pipe portion of the network are connected by at least one valve. The valve is formed of a bilayer strip. In response to change in temperature, the shape of the bilayer strip changes to move the valve from a substantially closed position to an open position. In one configuration, the change is irreversible. In another configuration, the change is reversible in response to an opposite change in temperature.

公开(公告)号：US09588538B2

公开(公告)日：2017-03-07

申请号：US14675309

申请日：2015-03-31

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Jean-Pierre Blanc ,  Pratap Narayan Singh

IPC: H05F3/02 ,  G05F3/16 ,  G05F3/26 ,  G05F3/30

CPC classification number: G05F3/16 ,  G05F3/26 ,  G05F3/267 ,  G05F3/30

Abstract: A reference voltage generation circuit, including a first current source in series with a first bipolar transistor; a second current source in series with a first resistor; a third current source in series with a second bipolar transistor, the third current source being assembled as a current mirror with the first current source; a second resistor between the base of the second bipolar transistor and the junction point between the current source and the first resistor; and a fourth current source in series with a third resistor, the junction point between the fourth current source and the third resistor defining a reference voltage terminal.

Abstract translation: 参考电压产生电路，包括与第一双极晶体管串联的第一电流源; 与第一电阻器串联的第二电流源; 与第二双极晶体管串联的第三电流源，所述第三电流源被组装为具有所述第一电流源的电流镜; 第二电阻器，位于第二双极晶体管的基极与电流源与第一电阻之间的连接点之间; 以及与第三电阻器串联的第四电流源，所述第四电流源和所述第三电阻器之间的连接点限定参考电压端子。

公开(公告)号：US20170059893A1

公开(公告)日：2017-03-02

申请号：US14836011

申请日：2015-08-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Patrick LEMAITRE ,  Jean-Francois CARPENTIER ,  Charles BAUDOT ,  Jean-Robert MANOUVRIER

IPC: G02F1/025 ,  G02B6/293

CPC classification number: G02F1/225 ,  G02F1/025 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2203/15

Abstract: An electro-optic (E/O) device includes an asymmetric optical coupler having an input and first and second outputs, a first optical waveguide arm coupled to the first output of the first asymmetric optical coupler, and a second optical waveguide arm coupled to the second output of the first asymmetric optical coupler. At least one E/O amplitude modulator is coupled to at least one of the first and second optical waveguide arms. An optical combiner is coupled to the first and second optical waveguide arms downstream from the at least one E/O amplitude modulator.

Abstract translation: 电光（E / O）装置包括具有输入和第一和第二输出的不对称光耦合器，耦合到第一非对称光耦合器的第一输出的第一光波导臂和耦合到第一和第二输出的第二光波导臂 第二非对称光耦合器的第二输出。 至少一个E / O振幅调制器耦合到第一和第二光波导臂中的至少一个。 光合成器耦合到至少一个E / O振幅调制器下游的第一和第二光波导臂。

公开(公告)号：US09557805B2

公开(公告)日：2017-01-31

申请号：US14279514

申请日：2014-05-16

Applicant: STMicroelectronics SA

Inventor： Fabien Todeschini ,  Christophe Planat ,  Patrizia Milazzo ,  Salvatore Tricomi ,  Séverin Trochut ,  Pascal Urard

IPC: G06F1/32 ,  H02J7/35

CPC classification number: G06F1/3293 ,  H02J7/35

Abstract: A power management circuit including, between a first terminal intended to be connected to an electric power generation source and a second terminal intended to be connected to a load to be powered, a linear regulator and a circuit capable of activating the linear regulator when the power supplied by said source is greater than a first threshold.

Abstract translation: 一种电力管理电路，包括在要连接到发电源的第一端子和旨在连接到要供电的负载的第二端子之间，线性调节器和能够在所述电力的情况下启动所述线性调节器的电路 由所述源提供的大于第一阈值。

公开(公告)号：US09530922B2

公开(公告)日：2016-12-27

申请号：US14496192

申请日：2014-09-25

Applicant: STMICROELECTRONICS SA

Inventor： Pascal Fonteneau

IPC: H01L31/111 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/11 ,  H01L31/02 ,  H01L27/12 ,  H01L31/028 ,  H01L31/105

CPC classification number: H01L31/1113 ,  H01L27/1203 ,  H01L31/02019 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/105 ,  H01L31/11 ,  H01L31/18 ,  Y02E10/547

Abstract: An overvoltage protection component may be in a SOI layer, a portion of the SOI layer forming the core of an optical waveguide. This component may be made of semiconductor regions of different doping types and/or levels, at least one of these regions corresponding to at least a portion of the waveguide core.

Abstract translation: 过电压保护组件可以在SOI层中，SOI层的一部分形成光波导的核心。 该组件可以由不同掺杂类型和/或电平的半导体区域制成，这些区域中的至少一个对应于波导芯的至少一部分。

公开(公告)号：US09520334B2

公开(公告)日：2016-12-13

申请号：US14155007

申请日：2014-01-14

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  Anne Lombardot

Inventor： Laurent-Luc Chapelon ,  Pascal Ancey ,  Sandrine Lhostis

IPC: H01L23/34 ,  H01L23/36 ,  H01L23/427 ,  H01L23/433 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L29/06

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Abstract translation: 集成结构包括支撑至少一个芯片的支撑件和附接到芯片的散热壳体。 壳体是导热的并具有与芯片兼容的热膨胀。 壳体还可以包括填充有相变材料的封闭空腔。

公开(公告)号：US20160351745A1

公开(公告)日：2016-12-01

申请号：US15163550

申请日：2016-05-24

Applicant: Commissariat à I'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics SA

Inventor： Laurent Frey ,  Michel Marty

IPC: H01L31/113 ,  H01L27/146 ,  H01L31/0232

CPC classification number: H01L31/1133 ,  H01L27/14603 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/107

Abstract: A photodetector including a photoelectric conversion structure made of a semiconductor material and, on a light-receiving surface of the conversion structure, a stack of first and second diffractive elements, the second element being above the first element, wherein: the first element includes at least one pad made of a material having an optical index n1, laterally surrounded with a region made of a material having an optical index n2 different from n1; the second element includes at least one pad made of a material having an optical index n3, laterally surrounded with a region made of a material having an optical index n4 different from n3; the pads of the first and second elements are substantially vertically aligned; and optical index differences n1−n2 and n3−n4 have opposite signs.

Abstract translation: 一种光电检测器，包括由半导体材料制成的光电转换结构，并且在所述转换结构的受光面上具有第一和第二衍射元件的叠层，所述第二元件位于所述第一元件之上，其中：所述第一元件包括在 由具有光学折射率n1的材料制成的至少一个垫片，用由具有不同于n1的光学折射率n2的材料制成的区域横向包围; 第二元件包括由具有光学折射率n3的材料制成的至少一个衬垫，其横向被由具有不同于n3的光学折射率n4的材料制成的区域包围; 第一和第二元件的焊盘基本垂直对齐; 并且光学折射率差n1-n2和n3-n4具有相反的符号。

公开(公告)号：US09507089B2

公开(公告)日：2016-11-29

申请号：US14804629

申请日：2015-07-21

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain Chantre ,  Sébastien Cremer

IPC: G02B6/12 ,  G02B6/10 ,  C03B37/022 ,  H01L21/00 ,  H01L31/102 ,  G02B6/136 ,  H01S5/343 ,  H01S5/026 ,  H01S5/02 ,  G02B6/132 ,  G02B6/42

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/4257 ,  G02B2006/121 ,  G02B2006/12121 ,  H01S5/0085 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/026 ,  H01S5/343

Abstract: A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.

Abstract translation: 制造包括硅层上的光子分量和由III-V族材料制成的激光的集成电路的方法包括提供位于位于支撑体上的第一绝缘层上的硅层。 第一沟槽被蚀刻穿过硅层并在第一绝缘层上停止，并且第一沟槽被氮化硅层覆盖。 第二沟槽被蚀刻通过硅层的一部分，并且第一和第二沟槽用平坦化的氧化硅填充。 该方法还包括去除支撑体和第一绝缘层，以及在硅层的后表面上接合包括III-V族异质结构的晶片。