公开(公告)号：US20130069241A1

公开(公告)日：2013-03-21

申请号：US13236952

申请日：2011-09-20

申请人： Yaojian Lin ,  Rui Huang ,  Heap Hoe Kuan ,  Seng Guan Chow

发明人： Yaojian Lin ,  Rui Huang ,  Heap Hoe Kuan ,  Seng Guan Chow

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/48

CPC分类号： H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/82385 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first insulating layer formed over a carrier. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer. Vias are formed through the second insulating layer. A second conductive layer is formed over the second insulating layer and extends into the vias. A semiconductor die is mounted to the second conductive layer. A bond wire is formed between a contact pad on the semiconductor die and the second conductive layer. The second conductive layer extends to a mounting site of the semiconductor die to minimize the bond wire span. An encapsulant is deposited over the semiconductor die. A portion of the first insulating layer is removed to expose the second conductive layer. A portion of the first conductive layer is removed to electrically isolate remaining portions of the first conductive layer.

摘要翻译： 半导体器件具有形成在载体上的第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一导电层上形成第二绝缘层。 通过第二绝缘层形成通孔。 第二导电层形成在第二绝缘层上并延伸到通孔中。 半导体管芯安装到第二导电层。 在半导体管芯上的接触焊盘和第二导电层之间形成接合线。 第二导电层延伸到半导体管芯的安装位置，以使接合线跨距最小化。 密封剂沉积在半导体管芯上。 去除第一绝缘层的一部分以露出第二导电层。 去除第一导电层的一部分以电隔离第一导电层的剩余部分。

公开(公告)号：US08378502B2

公开(公告)日：2013-02-19

申请号：US12912730

申请日：2010-10-26

申请人： Seng Guan Chow ,  Heap Hoe Kuan

发明人： Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L29/24 ,  H01L23/48

CPC分类号： H01L27/14618 ,  H01L2224/48227 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/10156 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit package system includes: an integrated circuit die including an image sensor system having interconnects connected thereto; and a transparent encapsulant on the integrated circuit die with portions of the interconnects exposed and with only the transparent encapsulant over the image sensor system to comprise an image sensor device.

摘要翻译： 集成电路封装系统包括：集成电路管芯，其包括具有连接到其上的互连的图像传感器系统; 以及集成电路管芯上的透明密封剂，其中部分互连件暴露，并且仅透明密封剂在图像传感器系统上，以包括图像传感器装置。

公开(公告)号：US08304880B2

公开(公告)日：2012-11-06

申请号：US12881983

申请日：2010-09-14

申请人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

发明人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

IPC分类号： H01L23/02

CPC分类号： H01L21/563 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; mounting a bottom integrated circuit over the bottom substrate; mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate; connecting a top interconnect between the bottom substrate and the top substrate; and forming an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供底部基板; 将底部集成电路安装在底部基板上; 在底部集成电路的与底部基板相对的一侧上安装顶部基板; 连接底部基板和顶部基板之间的顶部互连; 并且在底部基板和顶部基板之间形成底部填充层，底部填充层将顶部互连件封装在底部集成电路的周边外部。

公开(公告)号：US08299596B2

公开(公告)日：2012-10-30

申请号：US12968257

申请日：2010-12-14

申请人： Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a base device having a base circuit connector directly on the component side; attaching conformal interconnects, having the same pre-deformation height from the component side, directly on the component side and offset from the base device; and attaching a stack substrate having stack interconnects directly on the conformal interconnects, portions of the stack interconnects covered by the conformal interconnects having different deformation heights from the component side.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有元件侧的基底基板; 将具有基座电路连接器的基座装置直接安装在部件侧; 将与构件侧具有相同的预变形高度的共形互连件直接连接在元件侧并偏离基座装置; 以及将具有堆叠互连的堆叠衬底直接附接在所述共形互连上，所述堆叠互连的由组件侧具有不同变形高度的共形互连覆盖的部分。

公开(公告)号：US20120199971A1

公开(公告)日：2012-08-09

申请号：US13446741

申请日：2012-04-13

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

摘要翻译： 嵌入式半导体管芯封装通过使用粘合剂将框架载体安装到临时载体上而制成。 框架载体包括每个包括围绕腔的引线框架互连结构的管芯安装位置。 半导体管芯设置在每个腔中。 将密封剂沉积在模具上的空腔中。 封装互连结构形成在引线框架互连结构和密封剂上。 封装互连结构和引线框互连结构电连接到管芯。 帧载体被分成单独的嵌入式芯片封装。 半导体管芯可以垂直堆叠或并排放置在腔内。 嵌入式管芯封装可以通过引线框互连结构堆叠并电互连。 半导体器件可以安装到嵌入式裸片封装并且通过引线框互连结构电连接到裸片。

公开(公告)号：US08163597B2

公开(公告)日：2012-04-24

申请号：US12410312

申请日：2009-03-24

申请人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

发明人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03

摘要： A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.

摘要翻译： 通过在第一牺牲载体上形成导电层制成半导体器件。 在导电层上形成焊料凸块。 在第一载体，导电层和焊料凸块上沉积无流动的底部填充材料。 将半导体管芯或部件压缩成无流动底部填充材料以与导电层电接触。 无流动底部填充材料和第一焊料凸块的表面被平坦化。 第一互连结构形成在无流动底部填充材料的第一表面上。 第一互连结构电连接到焊料凸块。 第二牺牲载体安装在第一互连结构上。 第二互连结构形成在无流动底部填充材料的第二侧上。 第二互连结构电连接到第一焊料凸块。 半导体器件可以通过焊料凸块堆叠和电连接。

公开(公告)号：US08039311B2

公开(公告)日：2011-10-18

申请号：US12205841

申请日：2008-09-05

申请人： Heap Hoe Kuan ,  Rui Huang ,  Seng Guan Chow

发明人： Heap Hoe Kuan ,  Rui Huang ,  Seng Guan Chow

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package system includes: providing a semiconductor die with bonding pad on the semiconductor die; attaching the semiconductor die to an intermediate layer; attaching one end of a bonding wire to the bonding pad; forming a bonding ball at the other end of the bonding wire, the bonding ball being fully or partially embedded in the intermediate layer; encapsulating the semiconductor die, the bonding pad, the bonding wire, and a portion of the bonding ball with a mold compound; removing the intermediate layer, resulting in the bonding ball protruding from the exposed mold compound bottom surface; and conditioning the bonding ball.

摘要翻译： 半导体封装系统包括：在半导体管芯上提供具有焊盘的半导体管芯; 将半导体管芯附接到中间层; 将接合线的一端附接到所述接合焊盘; 在接合线的另一端形成接合球，接合球完全或部分地嵌入在中间层中; 用模具化合物封装半导体管芯，接合焊盘，接合线和接合球的一部分; 去除中间层，导致接合球从露出的模塑复合物底表面突出; 并调节粘结球。

公开(公告)号：US20110233726A1

公开(公告)日：2011-09-29

申请号：US13155312

申请日：2011-06-07

申请人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

发明人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L27/04

CPC分类号： H01L23/3128 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/24 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/6677 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.

摘要翻译： 半导体器件包括垂直设置在种子层上的导电柱，形成在导电柱上的保形绝缘层，以及形成在保形绝缘层上的共形导电层。 第一导电柱，保形绝缘层和共形导电层构成垂直取向的集成电容器。 半导体器件还包括安装在种子层上的半导体管芯或部件，沉积在半导体管芯或部件上并围绕保形导电层的密封剂，以及形成在密封剂的第一侧上的第一互连结构。 第一互连结构电连接到第二导电柱，并且包括集成的无源器件。 所述半导体器件还包括形成在所述密封剂的与密封剂的第一侧相对的第二侧上的第二互连结构。

公开(公告)号：US20110210436A1

公开(公告)日：2011-09-01

申请号：US12714431

申请日：2010-02-26

申请人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

发明人： Seng Guan Chow ,  Hin Hwa Goh ,  Rui Huang ,  Heap Hoe Kuan

IPC分类号： H01L25/065 ,  H01L21/60

CPC分类号： H01L25/105 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; attaching a base barrier on the base substrate adjacent a base perimeter thereof; mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier.

摘要翻译： 一种制造集成电路封装系统的方法，包括：提供基底; 将基底集成电路附接在基底基板上; 在基底基板上邻近其基部周边附接基底屏障; 将堆叠衬底安装在基底衬底上，所述堆叠衬底具有堆叠衬底孔，所述堆叠衬底在其上具有衬底间连接器; 并且通过封装衬底间连接器的堆叠衬底孔分配连接器底部填充物，由基底屏障防止的连接器底部填充物溢出。

公开(公告)号：US07993941B2

公开(公告)日：2011-08-09

申请号：US12329458

申请日：2008-12-05

申请人： Rui Huang ,  Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Rui Huang ,  Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L21/00

CPC分类号： H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.

摘要翻译： 使用包括基板和多个导电柱的预制柱载体制成半导体封装。 胶片密封剂设置在柱载体的基板上并且在导电柱周围。 半导体管芯安装到临时载体上。 将载体和临时载体压在一起以将半导体管芯嵌入膜密封剂中。 半导体管芯设置在膜密封剂中的导电柱之间。 卸载载体的临时载体和基板。 在膜密封剂的第一侧上形成第一电路堆积层。 第一电路堆积层电连接到导电柱。 第二电路堆积层形成在与第一侧相对的膜密封剂的第二侧上。 第二电路堆积层电连接到导电柱。