公开(公告)号：US20190172941A1

公开(公告)日：2019-06-06

申请号：US16304620

申请日：2016-07-02

Applicant: INTEL CORPORATION

Inventor： Willy RACHMADY ,  Sanaz K. GARDNER ,  Chandra S. MOHAPATRA ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775

Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.

公开(公告)号：US20190088747A1

公开(公告)日：2019-03-21

申请号：US16198725

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Niti GOEL ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Marko RADOSAVLIJEVIC ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/20

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US20180254778A1

公开(公告)日：2018-09-06

申请号：US15755021

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Van LE ,  Gilbert DEWEY ,  Jack T. KAVALIEROS

IPC: H03K19/00 ,  H03K19/094 ,  G06F1/32 ,  G06F17/50 ,  H01L27/02

CPC classification number: H03K19/0016 ,  G06F1/3203 ,  G06F17/5045 ,  G06F17/5068 ,  H01L27/0207 ,  H03K19/0008 ,  H03K19/0013 ,  H03K19/094

Abstract: A power gating switch is described at a local cell level of an integrated circuit die. In one example a plurality of logic cells have a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell. A power switch for each logic cell is coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell.

公开(公告)号：US20180158933A1

公开(公告)日：2018-06-07

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Matthew V. METZ ,  Willy RACHMADY ,  Marc C. FRENCH ,  Jack T. KAVALIEROS ,  Rafael RIOS ,  Seiyon KIM ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  James M. POWERS ,  Sherry R. TAFT

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US20180151702A1

公开(公告)日：2018-05-31

申请号：US15576251

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Gopinath BHIMARASETTI ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02546 ,  H01L23/49827 ,  H01L23/49838 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20180151684A1

公开(公告)日：2018-05-31

申请号：US15576253

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Rafael RIOS ,  Gilbert DEWEY ,  Scott B. CLENDENNING ,  Jack T. KAVALIEROS

IPC: H01L29/45 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66568 ,  H01L29/78

Abstract: An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.

公开(公告)号：US20180145077A1

公开(公告)日：2018-05-24

申请号：US15574820

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Anand S. MURTHY ,  Tahir GHANI ,  Willy RACHMADY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Glenn A. GLASS

IPC: H01L27/092 ,  H01L29/205 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/8258 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

公开(公告)号：US20180138289A1

公开(公告)日：2018-05-17

申请号：US15576666

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Jack T. KAVALIEROS ,  Sanaz K. GARDNER

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L27/092

CPC classification number: H01L29/6681 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/30612 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7853

Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20170317187A1

公开(公告)日：2017-11-02

申请号：US15528793

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Marc C. FRENCH ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/66742 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.

公开(公告)号：US20170154960A1

公开(公告)日：2017-06-01

申请号：US15429126

申请日：2017-02-09

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Seung Hoon SUNG

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  Y10S977/762 ,  Y10S977/89 ,  Y10S977/938

Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.