公开(公告)号：US20120092033A1

公开(公告)日：2012-04-19

申请号：US12903984

申请日：2010-10-13

申请人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： G01R31/00 ,  G01R27/00 ,  G01R29/26

CPC分类号： G01R31/2648 ,  G01R31/002 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2224/13

摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

摘要翻译： 提供了一种用于测试未封装的半导体晶片的测试结构。 测试结构包括耦合到半导体晶片的互连结构的施力部件。 力施加部件可操作以向半导体晶片施加力。 测试结构还包括耦合到互连结构的第一和第二测试部分。 第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。 第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

公开(公告)号：US20120018875A1

公开(公告)日：2012-01-26

申请号：US12840900

申请日：2010-07-21

申请人： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

发明人： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC分类号： H01L23/498

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/93 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81464 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.

摘要翻译： 模具包括金属焊盘，钝化层和钝化层上的图案化缓冲层。 图案化缓冲层包括彼此分离的多个离散部分。 在图案化缓冲层的开口和钝化层中的开口上形成凸块下冶金（UBM）。 在UBM上形成电耦合的金属凸块。

公开(公告)号：US07553736B2

公开(公告)日：2009-06-30

申请号：US11486891

申请日：2006-07-13

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen

IPC分类号： H01L21/20

CPC分类号： H01L21/31058

摘要： A method for increasing capacitances of capacitors and the resulting integrated structure are provided. The method includes providing a substrate, forming a low-k dielectric layer over the substrate wherein the low-k dielectric layer includes a capacitor region and a non-capacitor region, forming a capacitor in the capacitor region, forming a masking layer which masks the non-capacitor region while leaving the capacitor region exposed, performing a local treatment to increase a k value of the low-k dielectric layer in the capacitor region, and removing the masking layer.

摘要翻译： 提供了一种用于增加电容器的电容的方法和所得到的集成结构。 该方法包括提供衬底，在衬底上形成低k电介质层，其中低k电介质层包括电容器区域和非电容器区域，在电容器区域中形成电容器，形成屏蔽层 非电容器区域，同时使电容器区域露出，进行局部处理以增加电容器区域中的低k电介质层的ak值，并且去除掩模层。

公开(公告)号：US20080014706A1

公开(公告)日：2008-01-17

申请号：US11486891

申请日：2006-07-13

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen

IPC分类号： H01L21/20

CPC分类号： H01L21/31058

摘要： A method for increasing capacitances of capacitors and the resulting integrated structure are provided. The method includes providing a substrate, forming a low-k dielectric layer over the substrate wherein the low-k dielectric layer includes a capacitor region and a non-capacitor region, forming a capacitor in the capacitor region, forming a masking layer which masks the non-capacitor region while leaving the capacitor region exposed, performing a local treatment to increase a k value of the low-k dielectric layer in the capacitor region, and removing the masking layer.

摘要翻译： 提供了一种用于增加电容器的电容的方法和所得到的集成结构。 该方法包括提供衬底，在衬底上形成低k电介质层，其中低k电介质层包括电容器区域和非电容器区域，在电容器区域中形成电容器，形成屏蔽层 非电容器区域，同时使电容器区域露出，进行局部处理以增加电容器区域中的低k电介质层的ak值，并且去除掩模层。

公开(公告)号：US09093411B2

公开(公告)日：2015-07-28

申请号：US12984669

申请日：2011-01-05

申请人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

发明人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5383 ,  H01L24/05 ,  H01L29/0649 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/00

摘要： A pad structure in a semiconductor wafer for wafer testing is described. The pad structure includes at least two metal pads connected there-between by a plurality of conductive visa in one or more insulation layers. A plurality of contact bars in contact with the bottom-most metal pad extends substantially vertically from the bottom-most metal pad into the substrate. An isolation structure substantially surrounds the plurality of contact bars to isolate the pad structure.

摘要翻译： 描述用于晶片测试的半导体晶片中的焊盘结构。 焊盘结构包括至少两个连接在其上的金属焊盘，其间通过一个或多个绝缘层中的多个导电签证。 与最底部的金属焊盘接触的多个接触棒从最底部的金属焊盘基本垂直地延伸到衬底中。 隔离结构基本上围绕多个接触杆以隔离垫结构。

公开(公告)号：US09000876B2

公开(公告)日：2015-04-07

申请号：US13419272

申请日：2012-03-13

申请人： Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo ,  Jie Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu

发明人： Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo ,  Jie Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu

IPC分类号： H01F5/00 ,  H01F27/28 ,  H01F27/36 ,  H01L31/107 ,  H01L23/522 ,  H01L23/552 ,  H01L23/00 ,  H01L49/02 ,  H01L23/58

CPC分类号： H01L23/5227 ,  H01L21/768 ,  H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L24/03 ,  H01L24/11 ,  H01L28/10 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/06515 ,  Y10T29/4902

摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.

摘要翻译： 提供一种形成电感器件的电感器件和方法。 在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。 虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。

公开(公告)号：US08749043B2

公开(公告)日：2014-06-10

申请号：US13409756

申请日：2012-03-01

申请人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC分类号： H01L23/02 ,  H01L21/16

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11011 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/068 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

摘要翻译： 包装结构包括第一包装和第二包装通过引入连接到第二包装件上的导热基材提供改进的热传导和机械强度。 第一封装具有第一衬底和第一集成电路。 第二包装具有包含通孔的第二基板，其具有第一热膨胀系数。 第二封装还具有第二集成电路，其具有位于第二基板上的第二热膨胀系数。 第二热膨胀系数从第一热膨胀系数偏离每摄氏度小于约10或小于约5百万分之一。 第一组导电元件将第一基板和第二基板连接。 第二组导电元件将第二基板和第二集成电路耦合。

公开(公告)号：US20130277838A1

公开(公告)日：2013-10-24

申请号：US13452507

申请日：2012-04-20

申请人： Chen-Hua Yu ,  Hao-Yi Tsai ,  Chien-Hsiun Lee ,  Chung-Shi Liu ,  Hsien-Wei Chen

发明人： Chen-Hua Yu ,  Hao-Yi Tsai ,  Chien-Hsiun Lee ,  Chung-Shi Liu ,  Hsien-Wei Chen

IPC分类号： H01L21/60 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/06 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2224/05552 ,  H01L2924/00

摘要： Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.

摘要翻译： 焊接方法和装置。 一种装置包括：在表面上具有导电端子的基板; 覆盖在衬底表面上的钝化层和导电端子; 所述钝化层中的开口暴露所述导电端子的一部分; 至少一个凸起凸块，其结合到所述开口中的所述导电端子并且沿垂直于所述基板的表面的方向延伸; 以及形成在所述开口中的所述导电端子上并且包围所述至少一个螺柱凸块的焊接连接。 公开了形成焊料连接的方法。

公开(公告)号：US20130228932A1

公开(公告)日：2013-09-05

申请号：US13409756

申请日：2012-03-01

申请人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11011 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/068 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

公开(公告)号：US09425112B2

公开(公告)日：2016-08-23

申请号：US13491364

申请日：2012-06-07

申请人： Jie Chen ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo

发明人： Jie Chen ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo

IPC分类号： G06F17/00 ,  G06F17/50 ,  H01L23/48 ,  H01L21/66 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L23/66 ,  G01R1/07328 ,  G01R35/005 ,  G06F17/5009 ,  H01L21/76822 ,  H01L22/34 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/13 ,  H01L28/10 ,  H01L2223/6627 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/19011 ,  H01L2924/1903 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.

摘要翻译： 一种方法包括测量晶片中的第一校准套件以获得第一性能数据。 晶片包括衬底，以及在衬底上的多个电介质层。 第一校准套件包括多个电介质层上的第一无源器件，其中在多个电介质层中基本上没有金属特征被布置在第一无源器件中。 该方法还包括测量晶片中的第二校准套件以获得第二性能数据。 第二校准套件包括与第一器件相同并且在多个电介质层上相同的第二无源器件，以及多个电介质层中的虚设图案并且被第二无源器件重叠。 第一性能数据和第二性能数据被去嵌入以确定多个介电层中的金属图案对覆盖无源器件的影响。