公开(公告)号：US06236112B1

公开(公告)日：2001-05-22

申请号：US09434113

申请日：1999-11-05

申请人： Michio Horiuchi ,  Takuya Kazama

发明人： Michio Horiuchi ,  Takuya Kazama

IPC分类号： H01L2144

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device having a semiconductor element and a connecting substrate, wherein the connecting substrate includes a flat sheet-like insulation member, having first and second surfaces. The first surface is provided with solder bumps projecting at locations corresponding to locations of electrodes on an electrode/terminal-formed face of the semiconductor element, or terminals formed at ends of patterned wirings formed by rerouting a conductive material on the electrode/terminal-formed fact. The second surface is provided with external connection terminals having a larger diameter than the solder bumps on the first surface and being electrically connected with the solder bumps through a via piercing the insulation member in the direction of its thickness. The semiconductor element is mounted on the connecting substrate by bonding the electrodes or the terminals on the electrode/terminal-formed face of the semiconductor element to the solder bumps.

摘要翻译： 一种具有半导体元件和连接基板的半导体器件，其中所述连接基板包括具有第一表面和第二表面的平坦片状绝缘部件。 第一表面设置有在与半导体元件的电极/端子形成面上的电极位置相对应的位置处突出的焊料凸块，或者形成在图案化布线的端部处形成的端子，其通过在电极/端子形成上重新布置导电材料而形成 事实。 第二表面设置有具有比第一表面上的焊料凸块更大的直径的外部连接端子，并且通过穿过该绝缘构件的厚度方向的通孔与焊料凸块电连接。 通过将半导体元件的电极/端子形成面上的电极或端子接合到焊料凸块，将半导体元件安装在连接基板上。

公开(公告)号：US06194668B1

公开(公告)日：2001-02-27

申请号：US09211806

申请日：1998-12-15

申请人： Michio Horiuchi ,  Yukiharu Takeuchi ,  Eiji Yoda

发明人： Michio Horiuchi ,  Yukiharu Takeuchi ,  Eiji Yoda

IPC分类号： H01R1204

CPC分类号： H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/10734

摘要： A multi-layer circuit board formed by laminating a plurality of circuit boards each having lands arranged in many number in the form of a lattice or in a staggering manner on the side of the mounting surface and having circuit patterns with the ends on one side thereof being connected to said lands and with the ends on the other side thereof being drawn toward the outside from a region where said lands are arranged; wherein the lands for drawing the circuit patterns in a number not less than a+1 are arranged on the oblique lines of an isosceles triangle having a base formed by consecutive lands of a number of n and having oblique lines in the diagonal directions, the value n satisfying m≧k+1 of the two values of: m={(land pitch)×(n−1)−(land diameter)−(space between patterns)}÷(pattern width+space between patterns), k=a(n−1)+(n−2), wherein “a” is the number of the circuit patterns that can be arranged between the neighboring lands on the circuit board, and “n” is a parameter.

摘要翻译： 一种多层电路板，其通过层叠多个电路板而形成，所述多个电路板具有以格子形式或以交错的方式布置在安装表面侧上的许多数量的焊盘，并且具有电路图案，其一侧的端部 连接到所述平台，并且其另一侧的端部从布置所述平台的区域向外侧拉出; 其中用于绘制不少于+ 1的数字的电路图案的焊盘布置在具有由n个并且在对角线方向上具有斜线的连续焊盘形成的基座的等腰三角形的斜线上， n满足以下两个值的m> = k + 1：其中“a”是可以布置在电路板上的相邻平台之间的电路图案的数量，“n”是参数。

公开(公告)号：US5943212A

公开(公告)日：1999-08-24

申请号：US841707

申请日：1997-04-30

申请人： Michio Horiuchi ,  Shigetsugu Muramatsu ,  Ryuichi Matsuki

发明人： Michio Horiuchi ,  Shigetsugu Muramatsu ,  Ryuichi Matsuki

IPC分类号： H01L23/15 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/40 ,  H05H7/20

CPC分类号： H05K1/0271 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/0133 ,  H05K3/4053 ,  Y10S428/901

摘要： Thermal stress caused by a difference in the coefficient of thermal expansion between the mounting substrate and the ceramic substrate acts little on the junction portions of the external connection terminals when a semiconductor device is mounted avoiding such problems that the junction portions are broken or peeled off the mounting substrate. An insulating buffer layer 40 is adhered onto the mounting surface of ceramic substrate 32 having required wiring patterns 34 onto where the external connection terminals 12 will be connected, the insulating buffer layer 40 having a Young's modulus smaller than that of a ceramic material of the ceramic substrate 32 and having electrically insulating property, terminal pads 14 are provided on the outer surface of the insulating buffer layer 40, and the terminal pads 14 and the wiring patterns 34 are electrically connected together through buffer conducting portions 42 provided penetrating through the insulating buffer layer 40 and having a Young's modulus nearly equal to that of the insulating buffer layer 40.

摘要翻译： 由于安装基板和陶瓷基板之间的热膨胀系数的差异导致的热应力在安装半导体器件时在外部连接端子的接合部分上几乎不起作用，从而避免了连接部分断开或剥离的问题 安装基板。 将绝缘缓冲层40粘附到具有所需布线图案34的陶瓷基板32的安装面上，连接到外部连接端子12上，绝缘缓冲层40的杨氏模量小于陶瓷的陶瓷材料 基板32并具有电绝缘性能，在绝缘缓冲层40的外表面上设置端子焊盘14，并且端子焊盘14和布线图案34通过穿过绝缘缓冲层的缓冲导电部分42电连接在一起 40，其杨氏模量几乎等于绝缘缓冲层40的杨氏模量。

公开(公告)号：US5702807A

公开(公告)日：1997-12-30

申请号：US734315

申请日：1996-10-21

申请人： Michio Horiuchi ,  Yoichi Harayama

发明人： Michio Horiuchi ,  Yoichi Harayama

IPC分类号： C04B35/64 ,  H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00

CPC分类号： H05K3/4061 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H05K1/092 ,  H05K1/0306 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1383 ,  H05K3/245 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A conductor circuit 12 made of aluminum is provided on a green sheet 10, the primary material of which is ceramic powder. The green sheets 10 are laminated and integrated into one body so that the conductor circuit 12 is not exposed onto the surface but is covered with the green sheet 10. The laminated body is fired at the firing temperature not lower than 660.degree. C. and a portion of the inner conductor circuit of the thus obtained sintered body is then exposed onto a surface of the substrate.

摘要翻译： 由铝制的导体电路12设置在生片10上，其主要材料是陶瓷粉末。 生片10被层叠并整合为一体，使得导体电路12不暴露在表面上，而是被生片10覆盖。层压体在不低于660℃的烧成温度下烧制， 然后将由此获得的烧结体的内部导体电路的一部分暴露在基板的表面上。

公开(公告)号：US5604018A

公开(公告)日：1997-02-18

申请号：US265028

申请日：1994-06-24

申请人： Michio Horiuchi ,  Yoichi Harayama

发明人： Michio Horiuchi ,  Yoichi Harayama

IPC分类号： H05K1/03 ,  B32B37/18 ,  H01L21/48 ,  H05K1/09 ,  H05K3/12 ,  H05K3/24 ,  H05K3/26 ,  H05K3/40 ,  H05K3/46 ,  B32B9/00

CPC分类号： B32B37/18 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/092 ,  H05K3/4061 ,  H05K1/0306 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1383 ,  H05K3/245 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T156/10 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/252

摘要： Internal wiring made of copper of low-resistance is provided in a ceramic oxide. Green sheets 10 made of oxide powder are provided with plane wiring 18 and/or via wiring 14 in which copper is used as wiring material. The green sheets 10 are laminated and integrated in such a manner that the wiring portions 4 and 18 are covered with the green sheet so as not to be exposed onto a surface. Then the laminated body is fired at a maximum temperature in a range from 1,083.degree. to 1,800.degree. C.

公开(公告)号：US4935390A

公开(公告)日：1990-06-19

申请号：US199332

申请日：1988-05-26

申请人： Michio Horiuchi ,  Kihou Mizushima ,  Shoichi Iwai

发明人： Michio Horiuchi ,  Kihou Mizushima ,  Shoichi Iwai

IPC分类号： C04B35/18 ,  C04B35/185

CPC分类号： C04B35/185

摘要： A sintered mullite-based body having an excellent dielectric constant and thermal expansion coefficient, and an improved flexural strength and surface smoothness, is obtained by heat treating a composition of 99.1 to 80% by weight of a mullite powder and 0.1 to 20% by weight of yttrium oxide as a sintering agent, optionally together with a colorant of MoO.sub.3.

摘要翻译： 通过热处理99.1〜80重量％的莫来石粉末和0.1〜20重量％的组合物，获得具有优异的介电常数和热膨胀系数以及改善的弯曲强度和表面光滑度的烧结莫来石基体 的氧化钇作为烧结剂，任选与MoO 3的着色剂一起。

公开(公告)号：US06849945B2

公开(公告)日：2005-02-01

申请号：US09881005

申请日：2001-06-14

申请人： Michio Horiuchi ,  Takashi Kurihara ,  Shigeru Mizuno

发明人： Michio Horiuchi ,  Takashi Kurihara ,  Shigeru Mizuno

IPC分类号： H01L23/12 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/5385 ,  H01L24/50 ,  H01L25/105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/00

摘要： To minimize a size of a semiconductor device and reduce a thickness thereof as well as improve the yield and lower the production cost in the production of a semiconductor package, a multi-layered semiconductor device is provided, wherein a film-like semiconductor package (10) incorporating therein a semiconductor chip (12) is disposed in a package accommodation opening (11a) of a circuit pattern layer to form a circuit board. A plurality of such circuit boards are layered together to electrically connect circuit patterns (13) of the circuit boards with each other via a low melting point metal (14) or lead beam bonding (13b).

摘要翻译： 为了最小化半导体器件的尺寸并减小其厚度，并且提高了半导体封装的制造中的产量并降低了生产成本，提供了一种多层半导体器件，其中膜状半导体封装（10 ）设置在电路图案层的封装容纳开口（11a）中以形成电路板。 多个这样的电路板层叠在一起，通过低熔点金属（14）或引线束接合（13b）将电路板的电路图案（13）彼此电连接。

公开(公告)号：US06518672B2

公开(公告)日：2003-02-11

申请号：US09880978

申请日：2001-06-14

申请人： Takashi Kurihara ,  Michio Horiuchi ,  Shigeru Mizuno ,  Yuka Tamadate

发明人： Takashi Kurihara ,  Michio Horiuchi ,  Shigeru Mizuno ,  Yuka Tamadate

IPC分类号： H01L2348

CPC分类号： H05K3/363 ,  H01L23/49805 ,  H01L23/4985 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H05K1/144 ,  H05K2201/0397 ,  H05K2201/10681

摘要： A multi-layer wiring substrate comprises: a plurality of wiring substrates, each of the substrates comprising a plate or sheet-like insulating layer and a wiring layer formed on only one of surfaces of the insulating layer; the plurality of wiring substrates being laminated in such a manner that the insulating layer and wiring layer are alternately arranged; at least a pair of said wiring layers arranged on respective surfaces of the insulating layer being electrically connected with each other by means of connecting portions formed so as to pass through the insulating layer; and the connecting portion comprises a part of the wiring layer which is extended into a region of an opening formed so as to pass through said insulating layer and a low-melting point metal disposed in the opening and electrically connecting the part of the wiring layer with a wiring substrate formed on an adjacent insulating layer of the laminated structure.

摘要翻译： 多层布线基板包括：多个布线基板，每个基板包括板或片状绝缘层和仅形成在绝缘层的一个表面上的布线层; 所述多个布线基板以使得所述绝缘层和布线层交替布置的方式层叠; 布置在绝缘层的各个表面上的至少一对所述布线层通过形成为穿过绝缘层的连接部彼此电连接; 并且所述连接部分包括延伸到形成为穿过所述绝缘层的开口的区域中的所述布线层的一部分和布置在所述开口中的低熔点金属，并且将所述布线层的所述部分与 形成在叠层结构的相邻绝缘层上的布线基板。

公开(公告)号：US06455786B1

公开(公告)日：2002-09-24

申请号：US09539117

申请日：2000-03-30

申请人： Michio Horiuchi ,  Shigetsugu Muramatsu ,  Shigeru Mizuno ,  Takashi Kurihara

发明人： Michio Horiuchi ,  Shigetsugu Muramatsu ,  Shigeru Mizuno ,  Takashi Kurihara

IPC分类号： H05K116

CPC分类号： H01L23/3114 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A wiring board and electrode of a semiconductor element are connected with each other by the method of wire bonding, and problems arising from the thermal stress generated in the process of mounting are overcome. There is provided a wiring board comprising: a first face joined to an electrode forming face of a semiconductor element 10; and a second face on the opposite side of the first face, a wiring pattern 16 being formed on the second face, a land 24 joined to an external connecting terminal 22 being formed at one end of the wiring pattern, a wire bonding section 16a connected with a bonding wire 40 being formed at the other end of the wiring pattern, wherein the land 24 is supported by a buffer layer 34 for reducing the thermal stress generated when the semiconductor element, to which the wiring board is attached, is mounted via the external connecting terminals, and the wire bonding section 16a is supported by a bonding support layer 36 having an elastic modulus capable of allowing wire bonding.

摘要翻译： 半导体元件的布线基板和电极通过引线接合的方式相互连接，克服了在安装过程中产生的热应力引起的问题。 提供了一种布线板，包括：连接到半导体元件10的电极形成面的第一面; 和在第一面的相对侧的第二面，形成在第二面上的布线图案16，形成在布线图案的一端的与外部连接端子22接合的台面24，连接有引线接合部16a 其中接合线40形成在布线图案的另一端，其中，台肩24由缓冲层34支撑，用于减小当安装有布线板的半导体元件经由 外部连接端子和引线接合部分16a由具有能够引线接合的弹性模量的接合支撑层36支撑。

公开(公告)号：US06407460B1

公开(公告)日：2002-06-18

申请号：US09616139

申请日：2000-07-13

申请人： Michio Horiuchi ,  Shigeru Mizuno

发明人： Michio Horiuchi ,  Shigeru Mizuno

IPC分类号： H01L2352

CPC分类号： H01L23/49838 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10734

摘要： The present invention provides a multilayer circuit board for mounting thereon a semiconductor chip or other electronic elements having electrode terminals or other connection terminals which are arranged in a grid, staggered, or close-packed manner in an improved form to enable reduction in the number of the wiring layers for lead wiring lines, thereby facilitating the production of multilayer circuit boards and providing an improved product reliability. The multilayer circuit board comprises: a base board having a mounting surface for mounting thereon a semiconductor chip and/or other electronic elements having lattice-arranged connection terminals; connection terminal pads arranged on the mounting surface to form a plane lattice corresponding to the lattice arrangement of the connection terminals and having lattice sites each occupied by one of the connection terminal pads; lead wiring lines lying on the mounting surface and having one end connected to the connection terminal pads and the other end extending outwardly from the plane lattice; and the said plane lattice having a peripheral zone including periodic vacant lattice areas formed by vacant lattice sites occupied by no connection terminal pads.

摘要翻译： 本发明提供了一种多层电路板，用于在其上安装半导体芯片或具有电极端子或其他连接端子的其他电子元件，电子端子或其他连接端子以改进的形式布置成格栅，交错或紧密堆叠的方式，以减少数量 用于引线布线的布线层，从而便于生产多层电路板并提供改进的产品可靠性。 多层电路板包括：基板，其具有用于安装其上的半导体芯片的安装表面和/或具有格子排列的连接端子的其它电子元件; 连接端子焊盘，其布置在所述安装表面上以形成与所述连接端子的格栅布置相对应的平面格子，并具有各自由所述连接端子焊盘之一占据的格子部位; 引线布线位于安装表面上，其一端连接到连接端子焊盘，另一端从平面格架向外延伸; 并且所述平面晶格具有包括由没有连接端子焊盘占据的空位网格形成的周期性空格格区域的周边区域。