公开(公告)号：US06774467B2

公开(公告)日：2004-08-10

申请号：US09812276

申请日：2001-03-20

申请人： Michio Horiuchi ,  Takashi Kurihara ,  Tomio Nagaoka ,  Masao Aoki ,  Shigeru Mizuno

发明人： Michio Horiuchi ,  Takashi Kurihara ,  Tomio Nagaoka ,  Masao Aoki ,  Shigeru Mizuno

IPC分类号： H01L23495

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665

摘要： Thin semiconductor device, especially a thin package, which reduces and achieves uniform mounting height, not requiring mounting of individual chips, improves manufacturing yield, without being affected by variation in chip thickness, enables testing alltogether, and process for producing same, the semiconductor mounted with back surface exposed upward, on top of an insulating substrate having throughholes in thickness direction, the area around semiconductor side surfaces being sealed by a resin layer, metal interconnections on the bottom surface of the substrate define bottom portions of throughholes of the substrate, a solder resist layer having throughholes in the thickness direction covers the bottom surface of metal interconnections and substrate, terminals extending downward from the active surface of the semiconductor are inserted into throughholes of the substrate, conductive filler fills gaps between the terminals and the throughholes of the substrate, and connection terminal and interconnections are electrically connected.

摘要翻译： 薄型半导体器件，特别是薄封装，其减少并实现均匀的安装高度，而不需要安装单个芯片，提高了制造成品率，而不受芯片厚度变化的影响，能够进行全面测试，以及制造工艺，半导体安装 背面向上露出，在厚度方向上具有通孔的绝缘基板的顶部，半导体侧面的周围的区域被树脂层密封，在基板的底面上的金属互连限定了基板的通孔的底部， 在厚度方向上具有通孔的阻焊层覆盖金属互连和基板的底面，从半导体的有源表面向下延伸的端子插入到基板的通孔中，导电填料填充端子之间的间隙和基板的通孔 ，连接终端 并且互连电连接。

公开(公告)号：US06849945B2

公开(公告)日：2005-02-01

申请号：US09881005

申请日：2001-06-14

申请人： Michio Horiuchi ,  Takashi Kurihara ,  Shigeru Mizuno

发明人： Michio Horiuchi ,  Takashi Kurihara ,  Shigeru Mizuno

IPC分类号： H01L23/12 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/5385 ,  H01L24/50 ,  H01L25/105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/00

摘要： To minimize a size of a semiconductor device and reduce a thickness thereof as well as improve the yield and lower the production cost in the production of a semiconductor package, a multi-layered semiconductor device is provided, wherein a film-like semiconductor package (10) incorporating therein a semiconductor chip (12) is disposed in a package accommodation opening (11a) of a circuit pattern layer to form a circuit board. A plurality of such circuit boards are layered together to electrically connect circuit patterns (13) of the circuit boards with each other via a low melting point metal (14) or lead beam bonding (13b).

摘要翻译： 为了最小化半导体器件的尺寸并减小其厚度，并且提高了半导体封装的制造中的产量并降低了生产成本，提供了一种多层半导体器件，其中膜状半导体封装（10 ）设置在电路图案层的封装容纳开口（11a）中以形成电路板。 多个这样的电路板层叠在一起，通过低熔点金属（14）或引线束接合（13b）将电路板的电路图案（13）彼此电连接。

公开(公告)号：US06518672B2

公开(公告)日：2003-02-11

申请号：US09880978

申请日：2001-06-14

申请人： Takashi Kurihara ,  Michio Horiuchi ,  Shigeru Mizuno ,  Yuka Tamadate

发明人： Takashi Kurihara ,  Michio Horiuchi ,  Shigeru Mizuno ,  Yuka Tamadate

IPC分类号： H01L2348

CPC分类号： H05K3/363 ,  H01L23/49805 ,  H01L23/4985 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H05K1/144 ,  H05K2201/0397 ,  H05K2201/10681

摘要： A multi-layer wiring substrate comprises: a plurality of wiring substrates, each of the substrates comprising a plate or sheet-like insulating layer and a wiring layer formed on only one of surfaces of the insulating layer; the plurality of wiring substrates being laminated in such a manner that the insulating layer and wiring layer are alternately arranged; at least a pair of said wiring layers arranged on respective surfaces of the insulating layer being electrically connected with each other by means of connecting portions formed so as to pass through the insulating layer; and the connecting portion comprises a part of the wiring layer which is extended into a region of an opening formed so as to pass through said insulating layer and a low-melting point metal disposed in the opening and electrically connecting the part of the wiring layer with a wiring substrate formed on an adjacent insulating layer of the laminated structure.

摘要翻译： 多层布线基板包括：多个布线基板，每个基板包括板或片状绝缘层和仅形成在绝缘层的一个表面上的布线层; 所述多个布线基板以使得所述绝缘层和布线层交替布置的方式层叠; 布置在绝缘层的各个表面上的至少一对所述布线层通过形成为穿过绝缘层的连接部彼此电连接; 并且所述连接部分包括延伸到形成为穿过所述绝缘层的开口的区域中的所述布线层的一部分和布置在所述开口中的低熔点金属，并且将所述布线层的所述部分与 形成在叠层结构的相邻绝缘层上的布线基板。

公开(公告)号：US06455786B1

公开(公告)日：2002-09-24

申请号：US09539117

申请日：2000-03-30

申请人： Michio Horiuchi ,  Shigetsugu Muramatsu ,  Shigeru Mizuno ,  Takashi Kurihara

发明人： Michio Horiuchi ,  Shigetsugu Muramatsu ,  Shigeru Mizuno ,  Takashi Kurihara

IPC分类号： H05K116

CPC分类号： H01L23/3114 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A wiring board and electrode of a semiconductor element are connected with each other by the method of wire bonding, and problems arising from the thermal stress generated in the process of mounting are overcome. There is provided a wiring board comprising: a first face joined to an electrode forming face of a semiconductor element 10; and a second face on the opposite side of the first face, a wiring pattern 16 being formed on the second face, a land 24 joined to an external connecting terminal 22 being formed at one end of the wiring pattern, a wire bonding section 16a connected with a bonding wire 40 being formed at the other end of the wiring pattern, wherein the land 24 is supported by a buffer layer 34 for reducing the thermal stress generated when the semiconductor element, to which the wiring board is attached, is mounted via the external connecting terminals, and the wire bonding section 16a is supported by a bonding support layer 36 having an elastic modulus capable of allowing wire bonding.

摘要翻译： 半导体元件的布线基板和电极通过引线接合的方式相互连接，克服了在安装过程中产生的热应力引起的问题。 提供了一种布线板，包括：连接到半导体元件10的电极形成面的第一面; 和在第一面的相对侧的第二面，形成在第二面上的布线图案16，形成在布线图案的一端的与外部连接端子22接合的台面24，连接有引线接合部16a 其中接合线40形成在布线图案的另一端，其中，台肩24由缓冲层34支撑，用于减小当安装有布线板的半导体元件经由 外部连接端子和引线接合部分16a由具有能够引线接合的弹性模量的接合支撑层36支撑。

公开(公告)号：US06407460B1

公开(公告)日：2002-06-18

申请号：US09616139

申请日：2000-07-13

申请人： Michio Horiuchi ,  Shigeru Mizuno

发明人： Michio Horiuchi ,  Shigeru Mizuno

IPC分类号： H01L2352

CPC分类号： H01L23/49838 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10734

摘要： The present invention provides a multilayer circuit board for mounting thereon a semiconductor chip or other electronic elements having electrode terminals or other connection terminals which are arranged in a grid, staggered, or close-packed manner in an improved form to enable reduction in the number of the wiring layers for lead wiring lines, thereby facilitating the production of multilayer circuit boards and providing an improved product reliability. The multilayer circuit board comprises: a base board having a mounting surface for mounting thereon a semiconductor chip and/or other electronic elements having lattice-arranged connection terminals; connection terminal pads arranged on the mounting surface to form a plane lattice corresponding to the lattice arrangement of the connection terminals and having lattice sites each occupied by one of the connection terminal pads; lead wiring lines lying on the mounting surface and having one end connected to the connection terminal pads and the other end extending outwardly from the plane lattice; and the said plane lattice having a peripheral zone including periodic vacant lattice areas formed by vacant lattice sites occupied by no connection terminal pads.

摘要翻译： 本发明提供了一种多层电路板，用于在其上安装半导体芯片或具有电极端子或其他连接端子的其他电子元件，电子端子或其他连接端子以改进的形式布置成格栅，交错或紧密堆叠的方式，以减少数量 用于引线布线的布线层，从而便于生产多层电路板并提供改进的产品可靠性。 多层电路板包括：基板，其具有用于安装其上的半导体芯片的安装表面和/或具有格子排列的连接端子的其它电子元件; 连接端子焊盘，其布置在所述安装表面上以形成与所述连接端子的格栅布置相对应的平面格子，并具有各自由所述连接端子焊盘之一占据的格子部位; 引线布线位于安装表面上，其一端连接到连接端子焊盘，另一端从平面格架向外延伸; 并且所述平面晶格具有包括由没有连接端子焊盘占据的空位网格形成的周期性空格格区域的周边区域。

公开(公告)号：US08729401B2

公开(公告)日：2014-05-20

申请号：US13032071

申请日：2011-02-22

申请人： Tomoo Yamasaki ,  Michio Horiuchi

发明人： Tomoo Yamasaki ,  Michio Horiuchi

IPC分类号： H05K1/03 ,  H05K1/16 ,  H05K1/11

CPC分类号： H05K3/4602 ,  H01L21/486 ,  H01L23/142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15724 ,  H05K3/4644 ,  H05K2201/10378 ,  H05K2203/0315 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A wiring substrate includes a composite substrate including an oxidized aluminum substrate portion in which a large number of penetration conductors penetrating in a thickness direction are provided, and a frame-like aluminum substrate portion provided around the oxidized aluminum substrate portion, and a wiring layer of n layers (n is an integer of 1 or more) connected to the penetration conductors.

摘要翻译： 布线基板包括复合基板，该复合基板包括设置有大量贯穿厚度方向的贯通导体的氧化铝基板部分和设置在氧化铝基板部分周围的框状铝基板部分，以及布线层 连接到穿透导体的n层（n为1以上的整数）。

公开(公告)号：US20130048350A1

公开(公告)日：2013-02-28

申请号：US13588013

申请日：2012-08-17

申请人： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda

发明人： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda

IPC分类号： H05K1/05

CPC分类号： H05K3/4608 ,  H05K1/0287 ,  H05K1/0306 ,  H05K3/002 ,  H05K3/4061 ,  H05K3/42 ,  H05K2201/09609

摘要： A base member includes: a core layer including: a plate-like body, made of aluminum oxide; and plural linear conductors, which penetrate through the plate-like body in a thickness direction of the plate-like body; a bonding layer, formed on at least one of a first surface and a second surface of the core layer; and a silicon layer or a glass layer, formed on the bonding layer.

摘要翻译： 基底构件包括：芯层，包括：由氧化铝制成的板状体; 以及在板状体的厚度方向上穿过板状体的多个线状导体; 形成在芯层的第一表面和第二表面中的至少一个上的结合层; 以及形成在所述接合层上的硅层或玻璃层。

公开(公告)号：US08362369B2

公开(公告)日：2013-01-29

申请号：US12792334

申请日：2010-06-02

申请人： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Masao Nakazawa

发明人： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Masao Nakazawa

IPC分类号： H05K1/11

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K1/0287 ,  H05K1/0306 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/09609 ,  H05K2201/09945 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring board includes a core substrate having a structure including an insulating base material and a large number of filamentous conductors densely provided in the insulating base material and piercing the insulating base material in a thickness direction thereof. Pads made of portions of wiring layers are oppositely disposed on both surfaces of the core substrate and electrically connected to opposite ends of a plurality of filamentous conductors in such a manner that the pads share the filamentous conductors. A wiring connection between one surface side and the other surface side of the core substrate is made through the pads. The insulating base material is made of an inorganic dielectric. Pads made of portions of the wiring layers are disposed on both surfaces of the core substrate and electrically connected only to corresponding one end sides of different groups each formed of a plurality of filamentous conductors.

摘要翻译： 布线基板包括芯基板，该芯基板具有密封地设置在绝缘基材中的绝缘基材和大量丝状导体，并且在其厚度方向上刺穿绝缘基材。 由布线层部分构成的垫相对地设置在芯基板的两个表面上，并且以多个丝状导体的相对端电连接，使得焊盘共享丝状导体。 通过焊盘制造芯基板的一个表面侧和另一个表面侧之间的布线连接。 绝缘基材由无机电介质制成。 由布线层的一部分制成的垫片设置在芯基板的两个表面上，并且仅电连接到由多个丝状导体形成的不同组的相应一端侧。

公开(公告)号：US08134444B2

公开(公告)日：2012-03-13

申请号：US12895915

申请日：2010-10-01

申请人： Michio Horiuchi ,  Yukio Shimizu ,  Kazunari Sekigawa ,  Tsuyoshi Kobayashi

发明人： Michio Horiuchi ,  Yukio Shimizu ,  Kazunari Sekigawa ,  Tsuyoshi Kobayashi

IPC分类号： H01F17/04 ,  H01R4/58

CPC分类号： H01F17/0013 ,  H01F41/041 ,  H01F2017/002 ,  Y10T29/4902

摘要： An inductor includes a core substrate including minute column-like electrical conductors extending between a front surface and a back surface of the core substrate. Each column-like electrical conductor is insulated from adjacent column-like electrical conductors by being surrounded by an insulating material. Insulation layers are formed on the front surface and the back surface of the core substrate, respectively. At least two connection electrical conductors extend through each of the insulation layers. Each connection electrical conductor is electrically connected to a plurality of the column-like electrical conductors. Wirings are formed on each of the insulation layers to connect said connection electrical conductors to each other electrically. The wirings, the connection electrical conductors and the column-like electrical conductors are connected to form a coil in a three-dimensional manner.

摘要翻译： 电感器包括芯基板，其包括在芯基板的前表面和后表面之间延伸的微小列状电导体。 每个柱状电导体被绝缘材料包围，与相邻的柱状电导体绝缘。 绝缘层分别形成在芯基板的前表面和后表面上。 至少两个连接电导体延伸穿过每个绝缘层。 每个连接电导体电连接到多个柱状电导体。 在每个绝缘层上形成布线，以将所述连接电导体彼此电连接。 连线，连接电导体和列状电导体被连接以形成三维方式的线圈。

公开(公告)号：US08057950B2

公开(公告)日：2011-11-15

申请号：US11419376

申请日：2006-05-19

申请人： Michio Horiuchi ,  Yasue Tokutake ,  Shigeaki Suganuma ,  Misa Watanabe

发明人： Michio Horiuchi ,  Yasue Tokutake ,  Shigeaki Suganuma ,  Misa Watanabe

IPC分类号： H01M8/10

CPC分类号： H01M4/8885 ,  H01M4/8621 ,  H01M4/8626 ,  H01M4/9025 ,  H01M8/1213 ,  H01M8/1246 ,  Y02E60/525 ,  Y02P70/56

摘要： A solid oxide fuel cell includes: a solid electrolyte; and electrodes on both surfaces of the solid electrolyte, wherein at least one of joint surfaces where the solid electrolyte and the electrodes are in contact with each other is a roughened surface having at least two different types of surface roughness.

摘要翻译： 固体氧化物燃料电池包括：固体电解质; 以及所述固体电解质的两面的电极，其中所述固体电解质和所述电极彼此接触的接合表面中的至少一个是具有至少两种不同类型的表面粗糙度的粗糙表面。