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公开(公告)号：US5943212A
公开(公告)日：1999-08-24
申请号：US841707
申请日：1997-04-30
CPC分类号： H05K1/0271 , H01L23/49816 , H01L23/49827 , H01L23/49894 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/12042 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H05K1/0306 , H05K1/113 , H05K2201/0133 , H05K3/4053 , Y10S428/901
摘要： Thermal stress caused by a difference in the coefficient of thermal expansion between the mounting substrate and the ceramic substrate acts little on the junction portions of the external connection terminals when a semiconductor device is mounted avoiding such problems that the junction portions are broken or peeled off the mounting substrate. An insulating buffer layer 40 is adhered onto the mounting surface of ceramic substrate 32 having required wiring patterns 34 onto where the external connection terminals 12 will be connected, the insulating buffer layer 40 having a Young's modulus smaller than that of a ceramic material of the ceramic substrate 32 and having electrically insulating property, terminal pads 14 are provided on the outer surface of the insulating buffer layer 40, and the terminal pads 14 and the wiring patterns 34 are electrically connected together through buffer conducting portions 42 provided penetrating through the insulating buffer layer 40 and having a Young's modulus nearly equal to that of the insulating buffer layer 40.
摘要翻译： 由于安装基板和陶瓷基板之间的热膨胀系数的差异导致的热应力在安装半导体器件时在外部连接端子的接合部分上几乎不起作用，从而避免了连接部分断开或剥离的问题 安装基板。 将绝缘缓冲层40粘附到具有所需布线图案34的陶瓷基板32的安装面上，连接到外部连接端子12上，绝缘缓冲层40的杨氏模量小于陶瓷的陶瓷材料 基板32并具有电绝缘性能，在绝缘缓冲层40的外表面上设置端子焊盘14，并且端子焊盘14和布线图案34通过穿过绝缘缓冲层的缓冲导电部分42电连接在一起 40，其杨氏模量几乎等于绝缘缓冲层40的杨氏模量。
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2.发明授权Substrate for inspecting electronic device, method of manufacturing substrate, and method of inspecting electronic device 失效用于检查电子装置的基板，基板的制造方法以及检查电子装置的方法公开(公告)号：US06404214B1
公开(公告)日：2002-06-11
申请号：US09468060
申请日：1999-12-20
IPC分类号： G01R3102
CPC分类号： H05K1/112 , G01R31/2886 , H01L2224/16237 , H05K1/0393 , H05K3/06 , H05K3/325 , H05K2201/0394 , H05K2201/09472 , H05K2201/10734
摘要： A substrate for inspecting an electronic device used for an electrical test of the electronic device having bump-shaped connection terminals, comprises: opening sections, the diameter of each opening being determined so that a connection terminal can be inserted into and drawn out from the opening, are formed penetrating the insulating substrate in a region on one side of an insulating substrate on which the electronic device is mounted, corresponding to an arrangement of the connection terminals; and wiring patterns, each of which is composed of a pad section being exposed onto a bottom face of the opening so that the pad can come into contact with the connection terminal so as to accomplish electrical continuity, a connecting pad section formed in a region outside of the region in which the pad section is formed, which comes into contact with a contact terminal of an inspection device so as to accomplish electrical continuity, and a wiring section for electrically connecting the pad section with the connecting pad section, are formed on the other side of the insulating substrate.
摘要翻译： 一种用于检查用于具有凸起形连接端子的电子设备的电气测试的电子设备的基板，包括：开口部分，每个开口的直径被确定为使得连接端子能够从开口插入和拉出 对应于连接端子的布置，在安装有电子设备的绝缘基板的一侧的区域中穿过绝缘基板; 以及布线图案，每个布线图案由暴露于开口的底面的焊盘部分组成，使得焊盘能够与连接端子接触以实现电连续性;连接焊盘部分形成在外部区域 形成有与检查装置的接触端子接触以实现电连续性的形成有焊盘部的区域，以及用于将焊盘部与连接焊盘部电连接的布线部，形成在 绝缘基板的另一侧。
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公开(公告)号：US06465886B1
公开(公告)日：2002-10-15
申请号：US09615558
申请日：2000-07-13
IPC分类号： H01L248
CPC分类号： H01L24/10 , H01L24/02 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/04042 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/00014 , H01L2924/00
摘要： Interconnection wiring lines connecting electrode terminals with external connection terminals are easily provided for semiconductor chips having increased number or density of external connection terminals as in/out terminals. A semiconductor device including a semiconductor chip having electrode terminals electrically connected to external connection terminals, the device comprising: a semiconductor chip having an electrode terminal carrying surface including electrode terminals and interconnection wiring lines, each of the interconnection wiring lines having one end bonded to one of the electrode terminals and the other end forming a pad; an insulating layer formed on the electrode terminal carrying surface to cover the electrode terminals, the interconnection wiring lines and the remaining area of the electrode terminal carrying surface; conductor lands formed on the insulating layer, each of the conductor lands having a part forming a via extending through the insulating layer to the pad of one of the interconnection wiring lines; and external connection terminals formed on the lands.
摘要翻译： 将具有外部连接端子的电极端子连接的互连线路容易地设置为具有作为输入/输出端子的外部连接端子的数量或密度增加的半导体芯片。 一种半导体器件，包括具有电连接到外部连接端子的电极端子的半导体芯片，该器件包括：具有包括电极端子和互连布线的电极端子承载表面的半导体芯片，每个互连配线的一端与一个 的电极端子，另一端形成焊盘; 绝缘层，形成在所述电极端子承载面上，以覆盖所述电极端子，所述互连布线和所述电极端子承载表面的剩余区域; 形成在所述绝缘层上的导体焊盘，每个所述导体焊盘具有形成穿过所述绝缘层延伸到所述互连布线之一的焊盘的部分的部分; 以及形成在焊盘上的外部连接端子。
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公开(公告)号：US06455786B1
公开(公告)日：2002-09-24
申请号：US09539117
申请日：2000-03-30
IPC分类号： H05K116
CPC分类号： H01L23/3114 , H01L23/3107 , H01L23/49827 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A wiring board and electrode of a semiconductor element are connected with each other by the method of wire bonding, and problems arising from the thermal stress generated in the process of mounting are overcome. There is provided a wiring board comprising: a first face joined to an electrode forming face of a semiconductor element 10; and a second face on the opposite side of the first face, a wiring pattern 16 being formed on the second face, a land 24 joined to an external connecting terminal 22 being formed at one end of the wiring pattern, a wire bonding section 16a connected with a bonding wire 40 being formed at the other end of the wiring pattern, wherein the land 24 is supported by a buffer layer 34 for reducing the thermal stress generated when the semiconductor element, to which the wiring board is attached, is mounted via the external connecting terminals, and the wire bonding section 16a is supported by a bonding support layer 36 having an elastic modulus capable of allowing wire bonding.
摘要翻译： 半导体元件的布线基板和电极通过引线接合的方式相互连接，克服了在安装过程中产生的热应力引起的问题。 提供了一种布线板，包括：连接到半导体元件10的电极形成面的第一面; 和在第一面的相对侧的第二面，形成在第二面上的布线图案16，形成在布线图案的一端的与外部连接端子22接合的台面24，连接有引线接合部16a 其中接合线40形成在布线图案的另一端，其中，台肩24由缓冲层34支撑，用于减小当安装有布线板的半导体元件经由 外部连接端子和引线接合部分16a由具有能够引线接合的弹性模量的接合支撑层36支撑。
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公开(公告)号：US06335493B1
公开(公告)日：2002-01-01
申请号：US09450140
申请日：1999-11-29
IPC分类号： H01R1204
CPC分类号： H05K1/112 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K3/3436 , H05K2201/09227 , H05K2201/10674 , H01L2224/05599
摘要： A multilayer wiring board for mounting a semiconductor chip or a semiconductor device, in which the number of wiring layers in minimized, having a plurality of wiring layers, in which each of said wiring layers includes lands arranged in the form of a square lattice and wiring patterns each having one end connected to one of said lands and the other end extending outward beyond an outermost row of said lattice, said lands having a land pitch p and a land diameter d and said wiring patterns having a pattern width w and an interpattern space s, said p, d, w, and s satisfying the following relationship: p−d
摘要翻译： 一种用于安装半导体芯片或半导体器件的多层布线板，其中具有多个布线层的布线层的数量最小化，其中每个所述布线层包括以正方形格子形式布置的布点和布线 每个图案的一端连接到所述平台之一并且另一端向外延伸超过所述格子的最外面的一行，所述平台具有平台间距p和平台直径d，并且所述布线图案具有图案宽度w和图案间距 s，所述p，d，w和s满足以下关系：并且其中所述格子具有周期性无地或空位格点，所述最外行中的所有土地具有从其向外延伸的布线图案，并且所述无平面或空格 位置提供了布线图案从其向外延伸的空间，并且所述无平面或空格格点位置提供了布线图案向外延伸的空间，并且是连接 到内陆的土地。
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公开(公告)号：US06256207B1
公开(公告)日：2001-07-03
申请号：US09347909
申请日：1999-07-06
IPC分类号： H05K118
CPC分类号： H01L23/3114 , H01L21/563 , H01L23/49827 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/15173 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： A chip-sized semiconductor device includes a semiconductor element having a plurality of electrodes and a plurality of connecting pads electrically connected to the respective electrodes. A connecting board includes a base substrate having a first surface and a second surface, a plurality of connecting holes extending from the first surface to the second surface, a plurality of lands formed on the first surface to close the respective connecting holes, the lands being arranged in conformity with positions of the connecting pads of the semiconductor element, each of the connecting pads having a surface area smaller than that of the land. The semiconductor element is mounted on the connecting board in such a manner that the connecting pads of the semiconductor element are electrically connected to the respective lands of the connecting board by means of a plurality of bumps, respectively. A plurality of external connecting terminals on the second surface of the base substrate to be in contact with the respective lands through the respective connectings holes.
摘要翻译： 芯片尺寸的半导体器件包括具有多个电极的半导体元件和电连接到各个电极的多个连接焊盘。 连接板包括具有第一表面和第二表面的基底基板，从第一表面延伸到第二表面的多个连接孔，形成在第一表面上以闭合各个连接孔的多个连接孔， 与半导体元件的连接焊盘的位置一致地布置，每个连接焊盘的表面积小于焊盘的表面积。 半导体元件以这样的方式安装在连接板上，使得半导体元件的连接焊盘分别通过多个凸块电连接到连接板的相应焊盘。 多个外部连接端子，位于基底基板的第二表面上，以通过相应的连接孔与相应的凸台相接触。
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公开(公告)号：US06242799B1
公开(公告)日：2001-06-05
申请号：US09192490
申请日：1998-11-17
IPC分类号： H01L2304
CPC分类号： H01L23/564 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L2224/29101 , H01L2224/2929 , H01L2224/2938 , H01L2224/29386 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/83101 , H01L2224/8319 , H01L2224/8385 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/12044 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/3025 , H05K1/0271 , H05K1/0353 , H05K1/0373 , H05K2201/0133 , H05K2201/0187 , H05K2201/0212 , H01L2924/00014 , H01L2924/00 , H01L2924/0503 , H01L2924/05442 , H01L2924/05432 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2924/20753
摘要： An anisotropic stress buffer includes a plate or sheet-like body having relatively low elastic modulus. A plurality of elements, each having relatively high elastic modulus, are contained in the plate or sheet-like body, in such a manner that the buffer has a characteristic as a high elastic modulus member having a Young's modulus higher than a predetermined value with respect to a compression stress in the thickness direction and also has a characteristic as a low elastic modulus member having a Young's modulus lower than the predetermined value with respect to a tension stress in the planar direction. A semiconductor device includes such a anisotropic stress buffer to which a semiconductor chip is adhered. Electrode terminals of the chip are electrically connected to a wiring pattern formed on the anisotropic stress buffer.
摘要翻译： 各向异性应力缓冲器包括具有相对较低弹性模量的板或片状体。 每个具有较高弹性模量的多个元件被包含在板或片状体中，使得缓冲器具有作为高弹性模量构件的特性，其杨氏模量高于预定值，相对于 相对于平面方向的拉伸应力，也具有作为低弹性模量构件的杨氏模量比规定值低的特性。 半导体器件包括粘附有半导体芯片的各向异性应力缓冲器。 芯片的电极端子电连接到形成在各向异性应力缓冲器上的布线图案。
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8.发明申请Wiring Substrate, Semiconductor Device, and Method for Manufacturing Wiring Substrate 有权接线基板，半导体器件和制造接线基板的方法公开(公告)号：US20110316170A1
公开(公告)日：2011-12-29
申请号：US13166083
申请日：2011-06-22
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/10175 , H01L2224/16225 , H01L2224/16227 , H01L2224/26175 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2924/01322 , H01L2924/15151 , H01L2924/00012 , H01L2924/00
摘要： A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion formed in a region corresponding to the recess, a portion formed outward from the recess, and a portion formed inward from the recess. The upper surface of the solder resist layer at the portion corresponding to the recess is higher than the upper surface of the pads but lower than the upper surfaces of the other portions of the solder resist layer.
摘要翻译： 布线基板包括在包括焊盘的最上层中的布线图案。 阻焊层覆盖布线图案。 凹陷使得阻焊层的部分布线图案露出以形成焊盘。 阻焊层包括形成在与凹部对应的区域中的部分，从凹部向外形成的部分和从凹部向内形成的部分。 阻焊层的与凹部对应的部分的上表面高于焊盘的上表面，但低于阻焊层的其它部分的上表面。
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公开(公告)号：US20110253422A1
公开(公告)日：2011-10-20
申请号：US13150691
申请日：2011-06-01
IPC分类号： H05K1/02
CPC分类号： H05K3/4007 , H05K1/111 , H05K3/0044 , H05K3/243 , H05K3/28 , H05K3/3452 , H05K3/4644 , H05K2201/0367 , H05K2201/0376 , H05K2201/09736 , H05K2203/025 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.
摘要翻译： 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度大于其最大布线层的厚度。
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10.发明授权公开(公告)号：US06628527B2
公开(公告)日：2003-09-30
申请号：US09741481
申请日：2000-12-20
IPC分类号： H05K702
CPC分类号： H01L23/13 , H01L24/97 , H01L25/0652 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16235 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/15331 , H05K1/141 , H05K1/144 , H05K1/182 , H05K3/3436 , H05K3/368 , H05K2201/09036 , H05K2201/10515 , H05K2201/10674 , Y10T29/4913 , Y10T29/49135 , H01L2224/81 , H01L2224/05599
摘要： A unit interconnection substrate for mounting leadless type electronic parts on a mount substrate by superposing them on each other in two or more stages, comprising an insulating surface on the top surface of which an interconnection circuit with conductor pads and connection terminals is formed, depressions for holding electronic parts formed in a bottom surface of the insulating substrate, connection terminals provided on the bottom surface of the insulating substrate on the periphery of the depression, and connection terminals electrically connected to the connection terminals of the top surface of the insulating substrate via conductor via holes provided in the insulating substrate. Electronic parts are electrically connected to the conductor pads on the top surface of the insulating substrate, thereby to make it possible to mount the electronic parts on the insulating substrate. Together with this, holding of the electronic parts mounted on the mount substrate in the depressions of the bottom surface of the insulating substrate is made possible.
摘要翻译： 一种单元互连基板，用于通过将安装基板上的无引线型电子部件彼此叠置在两个或更多个阶段中来安装无引线型电子部件，所述两个或多个阶段包括在其顶表面上形成有与导体焊盘和连接端子的互连电路的绝缘表面， 保持形成在所述绝缘基板的底面的电子部件，设置在所述凹部的周围的所述绝缘基板的底面上的连接端子，以及通过导体电连接到所述绝缘基板的上表面的连接端子的连接端子 通孔设置在绝缘基板中。 电子部件电连接到绝缘基板的顶表面上的导体焊盘，从而可以将电子部件安装在绝缘基板上。 与此同时，能够将安装在安装基板上的电子部件保持在绝缘基板的底面的凹部中。
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