公开(公告)号：US20180240704A1

公开(公告)日：2018-08-23

申请号：US15961212

申请日：2018-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/321 ,  H01L23/48 ,  H01L21/027 ,  H01L21/3105 ,  H01L29/66

CPC分类号： H01L21/76892 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/31055 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/481 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.

公开(公告)号：US10043753B2

公开(公告)日：2018-08-07

申请号：US15377592

申请日：2016-12-13

申请人： GLOBALFOUNDRIES INC.

发明人： Huy Cao ,  Zhiguo Sun ,  Joseph F. Shepard, Jr. ,  Moosung M. Chae

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/764 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

摘要： The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

公开(公告)号：US20180204760A1

公开(公告)日：2018-07-19

申请号：US15744018

申请日：2015-09-23

申请人： Intel Corporation

发明人： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Jasmeet S. (JZ) CHAWLA ,  Marie KRYSAK ,  Hui Jae YOO ,  Tristan A. TRONIC

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238

摘要： A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US20180196192A1

公开(公告)日：2018-07-12

申请号：US15653543

申请日：2017-07-19

申请人： Avary Holding (Shenzhen) Co., Limited. ,  HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.

发明人： XIAN-QIN HU ,  FU-YUN SHEN ,  MING-JAAN HO ,  FENG-YUAN HU

IPC分类号： H01P3/08

CPC分类号： G02B6/03694 ,  B32B27/38 ,  H01G4/06 ,  H01L21/7682 ,  H01L23/5225 ,  H01L23/53228 ,  H01L27/14623 ,  H01P3/08 ,  H01P3/085 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/024 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2203/063

摘要： A method for manufacturing high frequency signal transmission structure comprises: providing two dielectric layers, each of the two dielectric layers defining a top surface and a bottom surface and comprising a channel with a bottom open end opened at the top surface and a top open end opened at the bottom surface, an inner diameter of the each of the two channels gradually reducing further from the top open end to the bottom open end; providing a circuit layer with a transmission portion; providing two copper plates; combining the circuit layer, the two dielectric layers and the two copper plates to form a combination; providing a shielding layer around the two air chambers; and providing at least one solder mask covering the shielding layer. The present disclosure also provides a high frequency signal transmission structure obtained by the method.

公开(公告)号：US10008409B2

公开(公告)日：2018-06-26

申请号：US15713724

申请日：2017-09-25

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chich-Neng Chang ,  Ya-Jyuan Hung ,  Bin-Siang Tsai

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/535 ,  H01L2221/1063

摘要： A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.

公开(公告)号：US10008382B2

公开(公告)日：2018-06-26

申请号：US14813177

申请日：2015-07-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/52 ,  H01L29/06 ,  H01L21/02 ,  H01L21/76 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/02203 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L29/0649 ,  H01L2221/1047

摘要： The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

公开(公告)号：US20180174961A1

公开(公告)日：2018-06-21

申请号：US15893050

申请日：2018-02-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/311

CPC分类号： H01L23/5226 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device comprises a first protection layer over sidewalls and a bottom of a first trench in a first dielectric layer, a first barrier layer over the first protection layer, a first metal line in the first trench, a second protection layer over sidewalls and a bottom of a second trench in the first dielectric layer, a second barrier layer over the second protection layer, a second metal line in the first trench, an air gap between the first trench and the second trench and a third protection layer over sidewalls of a third trench in the first dielectric layer, wherein the first protection layer, the second protection layer and the third protection are formed of a same material.

公开(公告)号：US09994737B2

公开(公告)日：2018-06-12

申请号：US15389800

申请日：2016-12-23

申请人： Samsung Electronics Co., Ltd.

发明人： Sangkyun Kim ,  Yun-Jeong Kim ,  SeungHo Park

IPC分类号： H01L21/02 ,  C09G1/02 ,  H01L21/3105 ,  H01L21/768

CPC分类号： C09G1/02 ,  H01L21/02126 ,  H01L21/31055 ,  H01L21/31058 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76895

摘要： Provided are slurry compounds for polishing an SOH organic layer and methods of fabricating a semiconductor device using the same. The slurry compound may include a polishing particle, an oxidizing agent including at least one selected from the group consisting of a nitrate, a sulfate, a chlorate, a perchlorate, a chlorine, and a peroxide, and a polishing accelerator.

公开(公告)号：US20180158818A1

公开(公告)日：2018-06-07

申请号：US15786828

申请日：2017-10-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/49

CPC分类号： H01L27/0886 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L2221/1063

摘要： A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

公开(公告)号：US20180151504A1

公开(公告)日：2018-05-31

申请号：US15875212

申请日：2018-01-19

申请人： GLOBALFOUNDRIES INC.

发明人： Xunyuan ZHANG ,  Roderick A. AUGUR ,  Hoon KIM

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5221 ,  H01L23/53242 ,  H01L23/53295

摘要： The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.