公开(公告)号：US20240105569A1

公开(公告)日：2024-03-28

申请号：US18460623

申请日：2023-09-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ByungHyun KWAK

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  H01L23/31 ,  H01L23/544 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/544 ,  H01L25/105 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16225

Abstract: An integrated package and a method for making the same are provided. The integrated package includes: a first substrate including: a first interconnection area having a plurality of first interconnection structures; and a first alignment structure disposed outside the first interconnection area; a second substrate stacked above the first substrate and including: a second interconnection area having a plurality of second interconnection structures; and a second alignment structure disposed outside the second interconnection area, wherein the second alignment structure is substantially aligned with the first alignment structure in a stacking direction of the first substrate and the second substrate; and a connecting element disposed between the first substrate and the second substrate and configured for electrically connecting at least one of the plurality of first interconnection structures with at least one of the plurality of second interconnection structures.

公开(公告)号：US20240105551A1

公开(公告)日：2024-03-28

申请号：US17936075

申请日：2022-09-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Hyun-kyu Lee ,  Ji-seon Lee ,  Bum-ryul Maeng

IPC: H01L23/473 ,  H01L21/48

CPC classification number: H01L23/473 ,  H01L21/4871

Abstract: A semiconductor device includes a substrate. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor die. A first trench is formed in the encapsulant over the semiconductor die. A conductive layer is formed over the encapsulant and into the first trench.

公开(公告)号：US20240063194A1

公开(公告)日：2024-02-22

申请号：US17820502

申请日：2022-08-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： GunHyuck Lee ,  Yujeong Jang ,  Gayeun Kim ,  YoungUk Noh

IPC: H01L25/16 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/552 ,  H01L23/498 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/162 ,  H01L21/56 ,  H01L25/50 ,  H01L25/0655 ,  H01L23/552 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/16

Abstract: A semiconductor device has a first semiconductor package, second semiconductor package, and RDL. The first semiconductor package is disposed over a first surface of the RDL and the second semiconductor package is disposed over a second surface of the RDL opposite the first surface of the RDL. A carrier is initially disposed over the second surface of the RDL and removed after disposing the first semiconductor package over the first surface of the RDL. The first semiconductor package has a substrate, plurality of conductive pillars formed over the substrate, electrical component disposed over the substrate, and encapsulant deposited around the conductive pillars and electrical component. A shielding frame can be disposed around the electrical component. An antenna can be disposed over the first semiconductor package. A portion of the encapsulant is removed to planarize a surface of the encapsulant and expose the conductive pillars.

公开(公告)号：US20240055374A1

公开(公告)日：2024-02-15

申请号：US17819738

申请日：2022-08-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Peik Eng Ooi ,  Lee Sun Lim

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/02235 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/02311 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/13124 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13116 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/11849

Abstract: A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.

公开(公告)号：US20240021366A1

公开(公告)日：2024-01-18

申请号：US18353863

申请日：2023-07-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： KyoWang KOO ,  MinHee JEONG

IPC: H01G2/10 ,  H01L25/16 ,  H05K9/00 ,  H01F27/02 ,  H01F41/00 ,  H01C7/00 ,  H01C17/00

CPC classification number: H01G2/10 ,  H01L25/16 ,  H05K9/0024 ,  H01F27/022 ,  H01F41/005 ,  H01C7/00 ,  H01C17/00

Abstract: An electronic package comprises: a substrate; five-sided insulated electronic components, wherein each of the five-sided insulated electronic components comprises: a raw electronic component having a cuboid shape, wherein the raw electronic component has a bottom side at which the raw electronic component is mounted onto and connected with the substrate and five non-bottom sides; a conductive structure disposed on the bottom side of the raw electronic component; and an insulating layer disposed on the five non-bottom sides of the raw electronic component.

公开(公告)号：US11869848B2

公开(公告)日：2024-01-09

申请号：US17444853

申请日：2021-08-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： GunHyuck Lee

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L24/20 ,  H01L25/0652 ,  H01L2224/2205 ,  H01L2924/3025

Abstract: A semiconductor device has a first substrate and a first electrical component disposed over the first substrate. A first support frame is disposed over the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support brace extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shielding partition extending from the horizontal support channel to the first substrate. An encapsulant is deposited over the first electrical component and first substrate and around the first support frame. A second electrical component is disposed over the first electrical component. A second substrate is disposed over the first support frame. A second electrical component is disposed over the second substrate. A third substrate is disposed over the second substrate. A second support frame is disposed over the second substrate.

公开(公告)号：US20230411263A1

公开(公告)日：2023-12-21

申请号：US18332777

申请日：2023-06-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SooHan PARK ,  KyungEun KIM ,  YouJin SHIN ,  HyeSun KIM

IPC: H01L23/498 ,  H01L25/16 ,  H01L25/03 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L25/16 ,  H01L25/03 ,  H01L21/568 ,  H01L21/561 ,  H01L24/24 ,  H01L24/96 ,  H01L24/82 ,  H01L25/50 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/5385 ,  H01L2224/96 ,  H01L2224/24155 ,  H01L2224/24101 ,  H01L2224/82105 ,  H01L2224/2402 ,  H01L2224/82005

Abstract: A modular semiconductor device comprises: an encapsulant layer with an encapsulant bottom surface and an encapsulant top surface, wherein the encapsulant layer comprises a component region and an interlayer connection region; wherein the semiconductor component comprises a component conductive pattern exposed from the encapsulant bottom surface; an interlayer connection array disposed within the interlayer connection region, wherein the interlayer connection array comprises one or more conductive vias each extending between the encapsulant bottom surface and the encapsulant top surface; and an interposer layer laminated on the encapsulant layer and having an interposer bottom surface and an interposer top surface, wherein the interposer top surface is in contact with the encapsulant bottom surface; wherein the interposer layer comprises an interposer conductive pattern on the interposer bottom surface, and an interposer interconnection structure electrically coupled to the component conductive pattern, the interposer conductive pattern and the one or more conductive vias.

公开(公告)号：US20230402399A1

公开(公告)日：2023-12-14

申请号：US18329605

申请日：2023-06-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SeungHyun LEE ,  KyungHwan KIM ,  HongKyu PARK ,  InHo SEO ,  MyungGyu JIN

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L23/36

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L21/56 ,  H01L23/36

Abstract: A semiconductor device comprises a substrate, at least one electronic component mounted on the substrate, an encapsulant formed on the substrate and at least partially encapsulating the at least one electronic component, a shielding layer formed on the encapsulant, a thermal interface layer formed on the shielding layer, and a metal lid formed on the thermal interface layer.

公开(公告)号：US20230402344A1

公开(公告)日：2023-12-14

申请号：US18330347

申请日：2023-06-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SooHan PARK ,  HyeSun KIM ,  KyungEun KIM ,  YouJin SHIN

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/50

CPC classification number: H01L23/3675 ,  H01L24/32 ,  H01L21/50 ,  H01L2224/32245

Abstract: Provided is a heat spreader for use with a semiconductor device comprising a substrate and at least one semiconductor die mounted on the substrate. The heat spreader comprises: a main body defining a space for receiving the at least one semiconductor die; and two foot supports extending downward from the main body and opposite to each other, each of the foot supports defining a slot at its inner surface, wherein the slots of the two foot supports are aligned with each other. When the heat spreader is mounted with the semiconductor device, the slots prevent the substrate from moving closer to or away from the main body.

公开(公告)号：US20230369165A1

公开(公告)日：2023-11-16

申请号：US18315496

申请日：2023-05-10

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SooHan PARK ,  KyungEun KIM ,  YoSep PARK ,  InWeon RA

IPC: H01L23/40 ,  H01L23/495 ,  H01L23/13 ,  H01L21/60

CPC classification number: H01L23/40 ,  H01L23/49562 ,  H01L23/13 ,  H01L21/60

Abstract: A heat spreader can be used with a semiconductor component. The heat spreader includes: a body having a bottom surface to be in thermal contact with the semiconductor component, and a top surface opposite to the bottom surface; a plurality of holes disposed at a non-peripheral region of the body, wherein each hole passes through the body between the top surface and the bottom surface; and a plurality of extensions each being disposed within one of the plurality of holes and extending from the top surface and downward below the bottom surface, wherein the plurality of extensions are configured to hold the semiconductor component when the heat spreader is mounted with the semiconductor component.