公开(公告)号：US5237198A

公开(公告)日：1993-08-17

申请号：US860271

申请日：1992-04-01

Applicant: Ho-Jin Lee

Inventor： Ho-Jin Lee

IPC: H01L27/082 ,  H01L29/735 ,  H03F1/52

CPC classification number: H01L27/0821 ,  H01L29/735 ,  H03F1/52

Abstract: A lateral PNP transistor having either of the collector or the emitter diffusion layers layered with an n.sup.+ type diffusion layer, is shown. The added layer serves to increase the static electricity withstand stress along a transistor discharging path. A low withstand stress contributes to transistor damage at high breakdown voltages. When an n.sup.+ diffusion layer is formed within a diffusion layer in a lateral PNP transistor the transistor behaves as a combination of two transistors, PNP and NPN, selectively configured.

Abstract translation: 示出了具有与n +型扩散层层叠的集电极或发射极扩散层中的任一个的横向PNP晶体管。 添加的层用于增加沿着晶体管放电路径的静电耐受应力。 低耐受应力有助于在高击穿电压下的晶体管损坏。 当在横向PNP晶体管中的扩散层内形成n +扩散层时，晶体管作为两个晶体管（PNP和NPN）的组合进行选择性配置。

公开(公告)号：US09859191B2

公开(公告)日：2018-01-02

申请号：US15065903

申请日：2016-03-10

Applicant: Ho-Jin Lee ,  Byung Lyul Park ,  Jin Ho An

Inventor： Ho-Jin Lee ,  Byung Lyul Park ,  Jin Ho An

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/538 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor substrate, a circuit layer including an interlayer insulating layer on an upper surface of the substrate, and a conductive via penetrating through the interlayer insulating layer and the substrate, and electrically connected to the circuit layer. The device further includes an insulating layer surrounding the conductive via, and located between the conductive via and the substrate and between the conductive via and interlayer insulating layer, and a buffer layer located between the insulating layer and the conductive via, and overlapping at least a portion of the interlayer insulating layer in a depth direction of the conductive via.

公开(公告)号：US20170047270A1

公开(公告)日：2017-02-16

申请号：US15204632

申请日：2016-07-07

Applicant: Ho-Jin Lee ,  Byung Lyul Park ,  Kwangjin Moon ,  Jisoon Park ,  Jin Ho An

Inventor： Ho-Jin Lee ,  Byung Lyul Park ,  Kwangjin Moon ,  Jisoon Park ,  Jin Ho An

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

Abstract translation: 本文提供了具有通孔电极的半导体器件及其制造方法。 所述方法可以包括提供具有彼此面对的顶表面和底表面的半导体衬底，在半导体衬底的顶表面上形成具有中空圆柱形结构的主通孔和连接到主通路的金属线，在其上形成层间绝缘层 半导体衬底的顶表面覆盖主通孔和金属线，去除半导体衬底的一部分以形成露出主通孔的底表面的一部分的通孔，并且在通孔中形成通孔 电连接到主通路。 当在平面图中观察时，主通孔的底表面与通孔的圆周重叠。

公开(公告)号：US09153489B2

公开(公告)日：2015-10-06

申请号：US13474992

申请日：2012-05-18

Applicant: Ho-Jin Lee ,  Byung Lyul Park ,  SeYoung Jeong ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Byung Lyul Park ,  SeYoung Jeong ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025

Abstract: A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

Abstract translation: 微电子器件包括：衬底，其具有在其活性表面与其与有源表面相对的非活性表面之间延伸穿过的沟槽;在沟槽的侧壁之间延伸通过衬底的导电通孔电极，以及沿沟槽的非活性表面延伸的绝缘层 衬底在沟槽外部并且至少部分地延伸到沟槽中。 绝缘层限定沟槽中的间隙区域，其分离衬底和通孔电极。 还讨论了相关装置和制造方法。

公开(公告)号：US08952543B2

公开(公告)日：2015-02-10

申请号：US13718580

申请日：2012-12-18

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Byung-Lyul Park ,  Hyun-Soo Chung ,  Gil-Heyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Byung-Lyul Park ,  Hyun-Soo Chung ,  Gil-Heyun Choi

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.

Abstract translation: 一种半导体器件，包括下层，在下层的第一侧上的绝缘层，绝缘层中的互连结构，下层中的通孔结构。 通孔结构突出到绝缘层和互连结构中。

公开(公告)号：US08592988B2

公开(公告)日：2013-11-26

申请号：US13186049

申请日：2011-07-19

Applicant: Ho-Jin Lee ,  Sung-Dong Cho ,  Se-Young Jeong ,  Yeong-Lyeol Park ,  Sin-Woo Kang

Inventor： Ho-Jin Lee ,  Sung-Dong Cho ,  Se-Young Jeong ,  Yeong-Lyeol Park ,  Sin-Woo Kang

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.

Abstract translation: 半导体器件可以包括衬底和通孔。 衬底可以具有与第一表面相对的第一表面和第二表面，所述衬底包括形成在第一表面上的电路图案。 贯通电极穿透基板并且可以电连接到电路图案，所述通孔包括在基板的厚度方向上从第一表面延伸的第一插塞和在厚度方向上从第二表面延伸的第二插塞 以便连接到第一插头。

公开(公告)号：US08564139B2

公开(公告)日：2013-10-22

申请号：US13610068

申请日：2012-09-11

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/3192 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern.

Abstract translation: 提供半导体器件及其制造方法。 所述器件可以包括半导体衬底，设置在所述半导体衬底中以在所述半导体衬底的表面电平处具有第一宽度的第一导电图案，覆盖所述第一导电图案并具有基本上大于所述第一宽度的第二宽度的阻挡图案 ，部分地覆盖所述阻挡图案并且具有基本上小于所述第二宽度的第三宽度的第二导电图案，以及设置在所述第二导电图案的侧壁上的绝缘图案。 第二宽度可以基本上等于或小于绝缘图案的第三宽度和宽度之和。

公开(公告)号：US20130134603A1

公开(公告)日：2013-05-30

申请号：US13610068

申请日：2012-09-11

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/3192 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern.

Abstract translation: 提供半导体器件及其制造方法。 所述器件可以包括半导体衬底，设置在所述半导体衬底中以在所述半导体衬底的表面电平处具有第一宽度的第一导电图案，覆盖所述第一导电图案并具有基本上大于所述第一宽度的第二宽度的阻挡图案 ，部分地覆盖所述阻挡图案并且具有基本上小于所述第二宽度的第三宽度的第二导电图案，以及设置在所述第二导电图案的侧壁上的绝缘图案。 第二宽度可以基本上等于或小于绝缘图案的第三宽度和宽度之和。

公开(公告)号：US20120261821A1

公开(公告)日：2012-10-18

申请号：US13537953

申请日：2012-06-29

Applicant: Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

IPC: H01L23/488

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/01087

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

公开(公告)号：US08140707B2

公开(公告)日：2012-03-20

申请号：US12298426

申请日：2007-04-24

Applicant: Jang-Won Lee ,  Ho-Jin Lee ,  Sang-Man Bak

Inventor： Jang-Won Lee ,  Ho-Jin Lee ,  Sang-Man Bak

IPC: G06F15/173

CPC classification number: H04L65/1006 ,  H04L29/06027 ,  H04L29/12367 ,  H04L29/12528 ,  H04L29/12556 ,  H04L61/2514 ,  H04L61/2575 ,  H04L61/2585 ,  H04L65/103 ,  H04L65/104 ,  H04L65/1043

Abstract: Disclosed are examples of an interworking system. In some embodiments, the interworking system includes a STUN server and an application layer gateway (ALG) server. The STUN server can be configured to provide binding information. The application layer gateway (ALG) server can include an IP masquerading performer, a STUN client performer, an address translator and a determiner.

Abstract translation: 公开了互通系统的示例。 在一些实施例中，互通系统包括STUN服务器和应用层网关（ALG）服务器。 STUN服务器可以配置为提供绑定信息。 应用层网关（ALG）服务器可以包括IP伪装执行者，STUN客户端执行者，地址转换器和确定器。