公开(公告)号：US09894752B2

公开(公告)日：2018-02-13

申请号：US14678714

申请日：2015-04-03

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Kemal Aygun ,  Beom-Taek Lee

IPC: H01F27/28 ,  H01F41/04 ,  H05K1/02 ,  H05K1/16 ,  H01F17/00 ,  H05K1/11

CPC classification number: H05K1/0237 ,  H01F17/0013 ,  H01F2017/002 ,  H05K1/0233 ,  H05K1/116 ,  H05K1/165

Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

公开(公告)号：US09806011B2

公开(公告)日：2017-10-31

申请号：US14974726

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1517 ,  H01L2924/15311

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20170288290A1

公开(公告)日：2017-10-05

申请号：US15087802

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Adel A. Elsherbini ,  Kemal Aygun ,  Robert L. Sankman

IPC: H01P3/06 ,  H01B11/18 ,  G06F1/16

CPC classification number: H01P3/06 ,  G06F1/16 ,  H01B11/1891 ,  H01P3/02

Abstract: Electrical cable technology is disclosed. In one example, an electrical cable can include a transmission line conductor, a ground conductor, and a dielectric material. The dielectric material can have at least a portion with a thickness separating the transmission line conductor and the ground conductor that is variable along a length of the electrical cable. Such a non-uniform cable (e.g., a cable having components or features that vary in size and/or geometry along the length of the cable) can provide high IO density with acceptable conductive losses and cross-talk while maintaining a desired impedance.

公开(公告)号：US20170040264A1

公开(公告)日：2017-02-09

申请号：US15297005

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5381 ,  G06F17/5077 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及互连路由配置和相关技术。 在一个实施例中，一种装置包括基板，设置在基板上并具有第一多个迹线的第一布线层和与第一布线层直接相邻设置且具有第二多个迹线的第二布线层，其中第一布线层 第一多个迹线的迹线具有大于第二多个迹线的第二迹线的宽度的宽度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09478881B2

公开(公告)日：2016-10-25

申请号：US14642078

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Gaurav Chawla ,  Rajasekaran Swaminathan ,  Kemal Aygun ,  Li Sun

IPC: H01R13/193 ,  H01R12/51 ,  H01R12/70 ,  H01R43/20

CPC classification number: H01R12/7076 ,  H01R43/205 ,  H05K7/1038

Abstract: Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment, a socket assembly includes a socket body having a plurality of openings extending from a first side of the socket body to a second side of the socket body to provide an electrical pathway between the first side and the second side, the second side disposed opposite to the first side, wherein a holding portion of an individual opening of the plurality of openings adjacent to the first side of the socket body is shaped to hold a corresponding electrical contact of a die package by elastic force applied by the socket body to the electrical contact when the electrical contact is positioned within the holding portion. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于插座组件和相关技术和配置的卡扣连接器。 在一个实施例中，插座组件包括插座主体，该插座主体具有从插座本体的第一侧延伸到插座主体的第二侧的多个开口，以在第一侧和第二侧之间提供电路径，第二侧 与所述第一侧相对设置，其中所述多个开口的与所述插座主体的第一侧相邻的开口的保持部分成形为通过由所述插座主体施加的弹力来保持模具组件的对应电接触， 当电触点位于保持部分内时的电接触。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09397071B2

公开(公告)日：2016-07-19

申请号：US14102757

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H05K7/00 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

Abstract translation: 本说明书的微电子封装可以包括具有与其电连接的至少一行连接结构的第一微电子器件和具有与其电连接的至少一排连接结构的第二微电子器件，其中所述至少一个 第一微电子器件行与X方向上的至少一个第二微电子器件行内的对应连接结构对准。 包括具有在互连衬底的第一表面上沿x方向延伸的多个电隔离导电迹线的互连衬底的互连可以附接到所述至少一个第一微电子器件连接结构行和所述至少一个第二微电子器件 连接结构行，使得至少一个互连导电迹线形成第一微电子器件连接结构与其对应的第二微电子器件连接结构之间的连接。

公开(公告)号：US20240222321A1

公开(公告)日：2024-07-04

申请号：US18148533

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L2225/06548

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The second IC die is between the first IC die and the package substrate. The first IC die includes: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240113049A1

公开(公告)日：2024-04-04

申请号：US17937474

申请日：2022-10-03

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Cemil S. Geyik ,  Kemal Aygun ,  Tarek A. Ibrahim ,  Wei-Lun Jen ,  Zhiguo Qian ,  Dilan Seneviratne

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5386 ,  H01L21/486 ,  H01L2223/6616 ,  H01L2223/6627

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (IC) dies coupled to the package substrate on the first side. The plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.

公开(公告)号：US11923308B2

公开(公告)日：2024-03-05

申请号：US17114954

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5383 ,  H01L23/00 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/14

Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

公开(公告)号：US11887932B2

公开(公告)日：2024-01-30

申请号：US17684163

申请日：2022-03-01

Applicant: INTEL CORPORATION

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/762 ,  H01L25/065 ,  H01L29/06 ,  H01L21/765

CPC classification number: H01L23/5384 ,  H01L21/765 ,  H01L21/76283 ,  H01L25/0655 ,  H01L29/0649

Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.