公开(公告)号：US6072326A

公开(公告)日：2000-06-06

申请号：US916434

申请日：1997-08-22

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

IPC分类号： G01R1/04 ,  G01R31/02

CPC分类号： G01R1/0466 ,  G01R1/0433 ,  G01R1/0483

摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

公开(公告)号：US6057597A

公开(公告)日：2000-05-02

申请号：US172451

申请日：1998-10-14

申请人： Warren M. Farnworth ,  David R. Hembree ,  Derek Gochnour ,  Salman Akram ,  John O. Jacobson ,  James M. Wark ,  Steven G. Thummel

发明人： Warren M. Farnworth ,  David R. Hembree ,  Derek Gochnour ,  Salman Akram ,  John O. Jacobson ,  James M. Wark ,  Steven G. Thummel

IPC分类号： H01L23/04 ,  H01L23/10 ,  H01L23/12

CPC分类号： H01L23/10 ,  H01L23/04 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195

摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.

摘要翻译： 半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。 盖可以用模制塑料或冲压金属预制，并使用固化的密封件​​附接到基底。 还可以通过基底提供孔，以在形成密封期间允许压力平衡。 盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。 在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

公开(公告)号：US6018249A

公开(公告)日：2000-01-25

申请号：US988433

申请日：1997-12-11

申请人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

发明人： Salman Akram ,  Warren M. Farnworth ,  David R. Hembree

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R31/02 ,  H01L21/66 ,  H01L23/12

CPC分类号： G01R1/04 ,  H01L2924/15311

摘要： A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.

公开(公告)号：US07225044B2

公开(公告)日：2007-05-29

申请号：US10705728

申请日：2003-11-10

申请人： William M. Hiatt ,  Warren M. Farnworth ,  David R. Hembree ,  Peter A. Benson

发明人： William M. Hiatt ,  Warren M. Farnworth ,  David R. Hembree ,  Peter A. Benson

IPC分类号： G06F19/00

CPC分类号： B29C64/35 ,  B29C64/135 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y50/02

摘要： A programmed material consolidation apparatus includes a support with a surface that receives at least one substrate and prevents unconsolidated material from contacting undesired regions, such as the bottom surface, of the at least one substrate. When a programmed material consolidation process is used to form one or more objects on or adjacent to a substrate, the substrate may be secured to a support surface. Additionally, unconsolidated material may be prevented from contacting one or more undesired areas of the substrate.

摘要翻译： 编程材料固结装置包括具有接收至少一个基底的表面的支撑件，并且防止未固结的材料接触至少一个基底的不期望的区域，例如底部表面。 当使用编程材料固结工艺在衬底上或邻近衬底上形成一个或多个物体时，衬底可固定到支撑表面。 此外，可以防止未固结的材料接触基底的一个或多个不期望的区域。

公开(公告)号：US07239933B2

公开(公告)日：2007-07-03

申请号：US10705409

申请日：2003-11-10

申请人： William M. Hiatt ,  Warren M. Farnworth ,  David R. Hembree ,  Peter A. Benson

发明人： William M. Hiatt ,  Warren M. Farnworth ,  David R. Hembree ,  Peter A. Benson

IPC分类号： G06F19/00 ,  H01L21/56 ,  H01L21/31

CPC分类号： B29C64/35 ,  B29C64/135 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y50/02

摘要： A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

摘要翻译： 编程材料合并装置包括与所述至少一个制造位置相关联的至少一个制造位置和材料固结系统。 至少一个制造位置可以被配置为接收一个或多个制造衬底，例如半导体衬底。 具有可移动或位置固定的照相机的机器视觉系统可以与至少一个制造场所和材料合并系统相关联。 清洁部件也可以与至少一个制造部位相关联。 清洁部件可以与至少一个制造部位共享一个或多个元件，或者可以与其分开。 编程材料合并装置还可以包括基板处理系统，其将制造基板放置在编程材料固结装置的适当位置。

公开(公告)号：US07833832B2

公开(公告)日：2010-11-16

申请号：US12412906

申请日：2009-03-27

申请人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree

发明人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree

IPC分类号： H01L21/00 ,  H01L29/06 ,  H05K1/03

CPC分类号： H01L23/3114 ,  B33Y70/00 ,  B81B7/0006 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L24/48 ,  H01L27/14618 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/45015 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/4813 ,  H01L2224/48471 ,  H01L2224/85045 ,  H01L2224/85207 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10T29/49147 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate contacts, and forming openings from a backside of the substrate aligned with the substrate contacts. The method can also include the steps of providing an interposer substrate (or alternately a second semiconductor substrate), forming projections on the interposer substrate (or on the second semiconductor substrate), and forming conductive vias in the projections. The method can also include the steps of placing the projections in physical contact with the openings, and placing the conductive vias in electrical contact with the substrate contacts. The method can also include the steps of bonding the conductive vias to the substrate contacts, and forming terminal contacts on the interposer substrate (or alternately on one of the semiconductor substrates) in electrical communication with the conductive vias.

摘要翻译： 用于通过互连制造半导体部件的方法可以包括以下步骤：提供具有衬底触点的半导体衬底，以及从与衬底触点对准的衬底的背面形成开口。 该方法还可以包括提供插入器衬底（或者替代地第二半导体衬底）的步骤，在插入器衬底（或第二半导体衬底上）上形成突起，并在突起中形成导电通孔。 该方法还可以包括以下步骤：将突起放置在与开口物理接触的位置，并且将导电通孔放置在与基板触点电接触的位置。 该方法还可以包括以下步骤：将导电通孔接合到基板触点，以及在内导体基板（或者替代地在其中一个半导体基板上）上形成与导电通孔电连通的端子触点。

公开(公告)号：US06628128B1

公开(公告)日：2003-09-30

申请号：US09651860

申请日：2000-08-30

申请人： Warren M. Farnworth ,  Derek J. Gochnour ,  David R. Hembree

发明人： Warren M. Farnworth ,  Derek J. Gochnour ,  David R. Hembree

IPC分类号： G01R3102

CPC分类号： H05K1/112 ,  G01R1/0483 ,  H05K3/325 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/10734

摘要： A BGA test socket for use in standard testing and burn-in testing of BGA dies and method for testing such dies is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dies can be reliably tested including chip scale packaged (“CSP”) BGA dies. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dies and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dies through closing the test socket before removing the die deposit probe.

公开(公告)号：US06619532B2

公开(公告)日：2003-09-16

申请号：US10196666

申请日：2002-07-15

申请人： David R. Hembree ,  Michael E. Hess ,  John O. Jacobson ,  Warren M. Farnworth ,  Alan G. Wood

发明人： David R. Hembree ,  Michael E. Hess ,  John O. Jacobson ,  Warren M. Farnworth ,  Alan G. Wood

IPC分类号： B23K2010

CPC分类号： B23K20/10 ,  B23K2101/38

摘要： A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.

摘要翻译： 用于将互连的穿刺型导电接触构件接合到裸半导体管芯的接合焊盘的机器和方法包括使用安装成振动模具和互连中的一个或两者的一个或两个超声波振动器。 超声能量的短轴向线性爆发使得接触构件能够以低得多的压缩力在接合焊盘的表面上刺穿硬氧化物层并且迅速地实现完全的穿透深度。

公开(公告)号：US06320397B1

公开(公告)日：2001-11-20

申请号：US08614735

申请日：1996-03-13

申请人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree

发明人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree

IPC分类号： G01R1073

CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/75 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/75 ,  H01L2224/85001 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49172 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

摘要： A carrier for testing an unpackaged semiconductor die is provided. The carrier includes a carrier base for supporting the die; an interconnect for establishing a temporary electrical connection with the die; and a force distribution mechanism for biasing the die and interconnect together. In an illustrative embodiment the carrier is formed with a laminated ceramic base. The ceramic base includes internal conductive lines that are wire bonded to the interconnect and metal plated external contacts that are connected to external test circuitry. In an alternate embodiment the carrier is formed with an injection molded plastic base and includes 3-D circuitry formed by a metallization and photolithographic process. In either case, the carrier is adapted for testing different die configurations by interchanging different interconnects.

摘要翻译： 提供了用于测试未封装的半导体管芯的载体。 载体包括用于支撑模具的载体基体; 用于建立与所述管芯的临时电连接的互连; 以及用于偏压模具并互连在一起的力分配机构。 在说明性实施例中，载体形成有层压陶瓷基底。 陶瓷基座包括内部导电线，引线连接到互连线和金属电镀外部触点，连接到外部测试电路。 在替代实施例中，载体由注射成型的塑料基底形成，并且包括通过金属化和光刻工艺形成的3-D电路。 在任一情况下，载体适于通过互换不同的互连来测试不同的管芯配置。

公开(公告)号：US5955877A

公开(公告)日：1999-09-21

申请号：US170844

申请日：1998-10-13

申请人： Warren M. Farnworth ,  Alan G. Wood ,  John O. Jacobson ,  David R. Hembree ,  James M. Wark ,  Jennifer L. Folaron ,  Robert J. Folaron ,  Jay C. Nelson ,  Lelan D. Warren

发明人： Warren M. Farnworth ,  Alan G. Wood ,  John O. Jacobson ,  David R. Hembree ,  James M. Wark ,  Jennifer L. Folaron ,  Robert J. Folaron ,  Jay C. Nelson ,  Lelan D. Warren

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/311 ,  H01L21/00 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H05K13/08

CPC分类号： H01L21/67276 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2893 ,  H01L21/67126 ,  H01L21/67242 ,  H01L21/67259 ,  H01L21/681 ,  H01L24/74 ,  H05K13/08 ,  G01R31/311 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49004 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178

摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).

摘要翻译： 从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。 采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。 本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。