Abstract:
An adhesive composition and methods incorporating the adhesive composition in semiconductor applications are provided. The adhesive composition is an instant setting adhesive composition that does not require external energy input such as heat or radiation such for application of the adhesive composition on a surface. The instant setting composition possesses sufficient thixotropic characteristics such that applying the instant setting adhesive composition to a surface can be accomplished by a variety of application techniques and in a variety of patterns. Once applied to the surface, the instant setting adhesive composition sets to retain the discrete pattern as applied, in a relatively short period of time, typically from about 0.10 to about 120 seconds at an ambient temperature, typically from 20° C. to 30° C. Advantageously, the instant setting adhesive composition can be screen printed on a semiconductor wafer prior to singulation because streets between the dice are essentially free of the instant setting adhesive composition.
Abstract:
Methods for attaching an integrated circuit die to a substrate. Specifically, substrates which are used for BOC/COB or F/C surface mounting comprise protrusions on the surface of the substrate. The protrusions are configured to form barriers to hold an adhesive paste within the barriers. An integrated circuit die is disposed on the top of the barriers and coupled to the substrate by the adhesive paste.
Abstract:
An apparatus and method for face-down connection of a die to a substrate with polymer electrodes, the method comprising forming a plurality of conductive polymer electrodes on a substrate assembly: and elevating the temperature of the die sufficiently to cause electrical and fixed connection of the die to the electrodes upon appropriate contact; and then bringing the die face and electrodes into appropriate contact thereby forming the fixed and electrical connection.
Abstract:
A multi-layered metal bond pad for a semiconductor die having a conductive metal layer and an overlying ruthenium electrode layer. The ruthenium electrode layer protects the conductive metal from oxidation due to ambient environmental conditions. An interconnect structure such as a wire bond or solder ball may be attached to the ruthenium layer to connect the semiconductor die to a lead frame or circuit support structure. Also disclosed are processes for forming the ruthenium layer.
Abstract:
A Z-axis electrical contact may be formed using a resinous deposit containing conductive particles which may align along surface regions to form an electrical conduction path over the resinous material. If the resinous material is thermoplastic, the material may be heated to mechanically bond to contact surfaces. Advantageously, the resinous material may be formed by forcing a resinous matrix containing conductive particles through an annular opening in a stencil. The resulting member allows surfaces to be contacted which may be irregular or may be covered by native oxide layers.
Abstract:
A microelectronic substrate assembly and method for manufacture. In one embodiment, bond members (such as solder balls) project away from a surface of the microelectronic substrate to define a fill region or cavity between the surface of the microelectronic substrate and the bond members. A fill material is disposed in the fill region, for example, by dipping the microelectronic substrate in reservoir of fill material so that a portion of the fill material remains attached to the microelectronic substrate. An exposed surface of the fill material is engaged with a support member, such as a printed circuit board, and the bond members are attached to corresponding bond pads on the support member. The microelectronic substrate and the fill material can then be encapsulated with an encapsulating material to form a device package.
Abstract:
A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.
Abstract:
A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided by a barrier, which extends across and partway down the tank. The solutions have different densities and therefore separate into different layers. In the illustrated embodiment, integrated circuits with patterned contact pads are passed through one of the upper compartments, in which oxide is removed from the contact pads. Continuing downward into the lower compartment and laterally beneath the barrier, a protective layer is selectively formed on the insulating layer surrounding the contact pads. As the integrated circuits are moved upwardly into the second upper compartment, a conducting monomer selectively forms on the contact pads prior to any exposure to air. The integrated circuits can then be transferred to an ozone chamber where polymerization results in a conductive passivation layer on the contact pad.
Abstract:
A ball grid array for a flip chip assembly. The ball grid array including a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at least one bump having a core material and an outer layer. The rigidity of the core material is greater than that of the material of the outer layer. Additionally, the melting temperature of the core material is higher than the material of the outer layer. By this arrangement, the core material with an outer layer provides bumps that are substantially uniform in height. In addition, the balls only procure marks or deformation to the core material during burn-in testing and reflow. Therefore, when bonding the semiconductor device to the substrate, the ball grid array provides sufficient electrical and mechanical connection despite any non-planarity in the active surface of the semiconductor device and the top surface of the substrate, and any differing height in the plurality of balls due to testing the semiconductor device.
Abstract:
A microelectronic substrate assembly and method for manufacture. In one embodiment, bond members (such as solder balls) project away from a surface of the microelectronic substrate to define a fill region or cavity between the surface of the microelectronic substrate and the bond members. A fill material is disposed in the fill region, for example, by dipping the microelectronic substrate in reservoir of fill material so that a portion of the fill material remains attached to the microelectronic substrate. An exposed surface of the fill material is engaged with a support member, such as a printed circuit board, and the bond members are attached to corresponding bond pads on the support member. The microelectronic substrate and the fill material can then be encapsulated with an encapsulating material to form a device package.