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219 条记录 (耗时 0.034 秒)

    Post-fuse blow corrosion prevention structure for copper fuses
    111.
    发明授权
    Post-fuse blow corrosion prevention structure for copper fuses 有权
    铜熔丝保险丝熔断防腐结构

    公开(公告)号：US06746947B2

    公开(公告)日：2004-06-08

    申请号：US10254277

    申请日：2002-09-25

    申请人： Timothy H. Daubenspeck ,  Daniel C. Edelstein ,  Robert M. Geffken ,  William T. Motsiff ,  Anthony K. Stamper ,  Steven H. Voldman

    发明人： Timothy H. Daubenspeck ,  Daniel C. Edelstein ,  Robert M. Geffken ,  William T. Motsiff ,  Anthony K. Stamper ,  Steven H. Voldman

    IPC分类号： H01L2144

    CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/76843 ,  H01L23/5258 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.

    摘要翻译： 公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。 使用镶嵌工艺完成制作。 金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面 在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。 金属结构可用作耐腐蚀保险丝。 金属结构也可以用作电阻元件。 高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。 电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。 电阻器结构可以形成在电介质槽的壁上。 该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。 电阻可以与MOSFET或其他结构串联。

    BEOL structures incorporating active devices and mechanical strength
    117.
    发明授权
    BEOL structures incorporating active devices and mechanical strength 有权
    包含有源器件和机械强度的BEOL结构

    公开(公告)号：US08624323B2

    公开(公告)日：2014-01-07

    申请号：US13149797

    申请日：2011-05-31

    申请人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

    发明人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L23/34 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

    摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

    摘要翻译： 单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。 半导体器件层没有与衬底接合或结合界面。 使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层 形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层 通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

    COPPER INTERCONNECT STRUCTURE AND ITS FORMATION
    118.
    发明申请
    COPPER INTERCONNECT STRUCTURE AND ITS FORMATION 有权
    铜连接结构及其形成

    公开(公告)号：US20130307150A1

    公开(公告)日：2013-11-21

    申请号：US13475526

    申请日：2012-05-18

    申请人： Daniel C. Edelstein ,  Takeshi Nogami ,  Christopher Parks ,  Tsong-Lin Tai

    发明人： Daniel C. Edelstein ,  Takeshi Nogami ,  Christopher Parks ,  Tsong-Lin Tai

    IPC分类号： H01L23/52 ,  H01L21/425

    CPC分类号： H01L23/53238 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/53209 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/76 ,  H01L24/82 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

    摘要翻译： 具有改进的电迁移阻力的结构及其制造方法。 具有改进的电迁移电阻的结构包括具有双层盖和介电覆盖层的体互连。 双层帽包括底部金属部分和顶部金属氧化物部分。 优选地，金属氧化物部分是MnO或MnSiO，金属部分是Mn或CuMn。 通过用杂质（在优选实施例中为Mn）掺杂互连，然后在互连的顶部处产生晶格缺陷来产生该结构。 这些缺陷驱使增加的杂质向互连顶表面迁移。 当形成电介质盖层时，一部分与分离的杂质反应，从而在互连上形成双层盖。 Cu表面的晶格缺陷可以通过等离子体处理，离子注入，压缩薄膜或其他方式产生。