公开(公告)号：US5929743A

公开(公告)日：1999-07-27

申请号：US745888

申请日：1996-11-08

Applicant: Michio Miyazaki ,  Haruyuki Takeuchi ,  Tadao Bekku

Inventor： Michio Miyazaki ,  Haruyuki Takeuchi ,  Tadao Bekku

IPC: H01C1/01 ,  H01C1/014 ,  H01C1/14 ,  H01C7/02 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01C7/10

CPC classification number: H01C1/01 ,  H01C1/014 ,  H01C1/1406 ,  H05K1/0201 ,  H05K1/181 ,  H05K2201/062 ,  H05K2201/10378 ,  H05K2201/10643 ,  H05K2201/10659 ,  H05K2201/2036 ,  H05K3/341 ,  Y02P70/611

Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.

公开(公告)号：US5831332A

公开(公告)日：1998-11-03

申请号：US739218

申请日：1996-10-29

Applicant: Michio Sono ,  Junichi Kasai ,  Masanori Yoshimoto ,  Kazuto Tsuji ,  Kouji Saito

Inventor： Michio Sono ,  Junichi Kasai ,  Masanori Yoshimoto ,  Kazuto Tsuji ,  Kouji Saito

IPC: H01L23/482 ,  H01L23/495 ,  H01L23/58 ,  H05K3/30 ,  H05K3/34

CPC classification number: H05K3/303 ,  H01L23/49555 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01079 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K3/3426 ,  Y02P70/613

Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.

公开(公告)号：US5643835A

公开(公告)日：1997-07-01

申请号：US602896

申请日：1996-02-16

Applicant: Chok J. Chia ,  Seng-Sooi Lim

Inventor： Chok J. Chia ,  Seng-Sooi Lim

IPC: H01L23/495 ,  H05K3/30 ,  H05K3/34 ,  H01L21/56 ,  H01L21/58 ,  H01L21/60

CPC classification number: H05K3/303 ,  H01L23/49541 ,  H01L2224/48091 ,  H01L2224/48247 ,  H05K2201/10303 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10962 ,  H05K2203/167 ,  H05K3/3421 ,  Y02P70/613 ,  Y10S438/975 ,  Y10T29/49121 ,  Y10T29/49133

Abstract: A process of mounting a semiconductor device and leadframe to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.

Abstract translation: 描述了将半导体器件和引线框架安装到印刷电路板的工艺。 该装置具有主体和从主体延伸的多个引线。 一个或多个对准特征形成在包装体的外部上，以保持装置相对于印刷线路板的精确对准。 对准特征是形成为包装体外部的引线框架的一部分的突片。 突片可以具有各种形状，并且可以设置有用于与诸如印刷线路板的下面的基板上的销对准的孔。 引脚和突片可以电连接。

公开(公告)号：US5564182A

公开(公告)日：1996-10-15

申请号：US438026

申请日：1995-05-08

Applicant: Shary Nassimi

Inventor： Shary Nassimi

IPC: H01C1/02 ,  H01L23/04 ,  H05K3/34

CPC classification number: H01C1/02 ,  H01L23/041 ,  H05K3/341 ,  H05K3/3415 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/10166 ,  H05K2201/10583 ,  H05K2201/10651 ,  H05K2201/10659 ,  H05K2203/0455 ,  H05K3/3447 ,  H05K3/3468 ,  Y02P70/613 ,  Y10T29/49142 ,  Y10T29/49144

Abstract: A method for installing an axial multiple connection component, for connecting to a circuit board, comprising a shell, the shell substantially cylindrical, having two opposite ends. Conducting leads extend from the opposite ends along the axis, for providing two isolated connections to other components on the circuit board. At least one contact ring encircles the shell with the axis at the center of the contact ring, and provides another connection to the other components on the circuit board. The conducting leads are inserted into lead holes on the circuit board, and the contact ring rests against a metallically plated through ring hole. The component is either manually solder utilizing a solder melting tool or alternatively wave soldered onto the circuit board, with the solder wicking up the plated through ring hole to the contact ring to make a good electrical contact therebetween.

Abstract translation: 一种用于安装用于连接到电路板的轴向多重连接部件的方法，包括壳体，壳体基本上为圆柱形，具有两个相对的端部。 导线从轴的相对端延伸，用于提供与电路板上其他部件的两个隔离连接。 至少一个接触环围绕壳体，轴线处于接触环的中心，并提供与电路板上其他部件的另一连接。 导电引线插入电路板上的导线孔中，接触环支撑在金属电镀通孔环上。 组件是使用焊料熔化工具手工焊接或者焊接到电路板上的焊料，焊料将电镀通孔环穿过接触环，以在它们之间形成良好的电接触。

公开(公告)号：US5563446A

公开(公告)日：1996-10-08

申请号：US187238

申请日：1994-01-25

Applicant: Chok J. Chia ,  Patrick Variot

Inventor： Chok J. Chia ,  Patrick Variot

IPC: H01L23/12 ,  H01L23/24 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L23/02

CPC classification number: H01L23/24 ,  H01L23/3128 ,  H01L23/49531 ,  H01L23/49811 ,  H01L23/49816 ,  H05K3/341 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K2201/10659 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

Abstract translation: 表面安装的集成电路管芯封装包括从封装的周边横向向外延伸的一组外围引线，并且还包括在封装的底部上的焊球阵列。 该布置通过利用外围引线和球栅阵列来提供更大数量的对封装的输入/输出连接，而不需要增加封装尺寸或减小导电互连的宽度。

公开(公告)号：US5309021A

公开(公告)日：1994-05-03

申请号：US961352

申请日：1992-10-15

Applicant: Haruo Shimamoto ,  Jun Shibata ,  Toru Tachikawa ,  Tetsuya Ueda ,  Hiroshi Seki

Inventor： Haruo Shimamoto ,  Jun Shibata ,  Toru Tachikawa ,  Tetsuya Ueda ,  Hiroshi Seki

IPC: H01L21/60 ,  H01L23/28 ,  H01L23/495 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34 ,  H01L39/02 ,  H01L23/58 ,  H01L23/12 ,  H01L23/48

CPC classification number: H01L23/49527 ,  H01L23/49517 ,  H05K3/341 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/0263 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K3/3426 ,  Y02P70/613

Abstract: A semiconductor device according to the present invention has reduced inductance on a power supply line, a grounding line, and signal lines. In this invention, to reduce the length of the power supply connection and that of the grounding connection, a power supply metal post and a grounding metal post are respectively provided on a power supply lead of a semiconductor chip and grounding lead of the semiconductor chip perpendicular to the leads. The metal posts protrude from the resin encapsulating the chip and are connected to lands or a conductive circuit pattern on a printed circuit board. Furthermore, a planar conductor commonly connecting the power supply or grounding potentials is provided.

Abstract translation: 根据本发明的半导体器件具有减小电源线，接地线和信号线上的电感。 在本发明中，为了减小电源连接的长度和接地连接的长度，分别在半导体芯片的电源引线和半导体芯片的接地引线垂直地设置电源金属柱和接地金属柱 到线索 金属柱从封装芯片的树脂突出，并连接到印刷电路板上的焊盘或导电电路图案。 此外，提供通常连接电源或接地电位的平面导体。

公开(公告)号：US5254871A

公开(公告)日：1993-10-19

申请号：US520546

申请日：1990-05-08

Applicant: Eric Benavides ,  Agnes Guilhot

Inventor： Eric Benavides ,  Agnes Guilhot

IPC: H01L23/057 ,  H01L23/495 ,  H01L23/58 ,  H01L23/64 ,  H05K3/34 ,  H01L23/02 ,  H01L23/12

CPC classification number: H01L23/057 ,  H01L23/49572 ,  H01L23/585 ,  H01L23/645 ,  H01L24/50 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K2201/10659 ,  H05K3/3421 ,  H05K3/3447

Abstract: The package (10) of the integrated circuit (11) includes a TAB carrier (12), the supply conductors (15b) of which comprise shielding elements between groups of signal conductors and have a length that is largely shunted via a corresponding potential conductor plane (26b) of the decoupling device (24) of the package.

Abstract translation: 集成电路（11）的封装（10）包括TAB载体（12），其供电导体（15b）包括信号导体组之间的屏蔽元件，并且具有通过相应的电位导体平面大量分流的长度 （26）的所述解耦装置（24）。

公开(公告)号：US3991347A

公开(公告)日：1976-11-09

申请号：US545939

申请日：1975-01-31

Applicant: Robert David Hollyday

Inventor： Robert David Hollyday

IPC: H05K1/02 ,  H05K3/34 ,  H05K3/40 ,  H05K1/04

CPC classification number: H05K3/341 ,  H05K1/0243 ,  H05K3/3415 ,  H05K2201/0305 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/09572 ,  H05K2201/1006 ,  H05K2201/10659 ,  H05K2201/10969 ,  H05K2203/0455 ,  H05K3/3447 ,  H05K3/3468 ,  H05K3/4038 ,  Y02P70/613

Abstract: A method of one step soldering of the outer diameter of a filter sleeve to a printed circuit board while soldering the leads thereto simultaneously as well as the completed filter assembly. The method comprises provided a printed circuit board having an electrically conductive coating on at least the upper surface with a portion of the conductor removed in the regions where leads from the filter to be positioned on the top surface of the printed circuit board are to extend through the printed circuit board for soldering. The printed circuit board includes apertures extending entirely therethrough, not only for the leads from the components positioned on the surface thereof, but also beneath filter sleeves positioned on the printed circuit board. The apertures in the printed circuit board are preferably coated with an electrically conductive material to provide better adherence for the solder during the soldering operation. In the event a conductive ground plane is to be utilized on the upper and lower surfaces of the printed circuit board, it is essential that the apertures beneath the filter sleeves be plated through.

Abstract translation: 将过滤器套筒的外径一步焊接到印刷电路板，同时将引线同时焊接到完整的过滤器组件上的方法。 该方法包括提供一种印刷电路板，其至少在上表面上具有导电涂层，其中一部分导体在位于印刷电路板的顶表面上的来自过滤器的引线延伸穿过的区域中被去除 用于焊接的印刷电路板。 印刷电路板包括完全贯穿其中的孔，不仅用于来自定位在其表面上的部件的引线，而且位于布置在印刷电路板上的过滤器套筒下方。 印刷电路板中的孔优选地涂覆有导电材料，以在焊接操作期间为焊料提供更好的附着性。 在印刷电路板的上表面和下表面上要使用导电接地平面的情况下，过滤器套筒下方的孔口必须通过电镀。

公开(公告)号：US20170273192A1

公开(公告)日：2017-09-21

申请号：US15613752

申请日：2017-06-05

Applicant: Japan Aviation Electronics Industry, Limited

Inventor： Junya SATO ,  Ryosuke MITSUI

IPC: H05K3/12 ,  C09D11/52 ,  C09D11/38 ,  H01R4/70 ,  H05K3/40 ,  H05K3/38 ,  H01R4/02 ,  H01R4/04 ,  H05K3/00

CPC classification number: H05K3/1291 ,  C09D11/037 ,  C09D11/14 ,  C09D11/322 ,  C09D11/38 ,  C09D11/52 ,  H01R4/026 ,  H01R4/04 ,  H01R4/70 ,  H01R12/52 ,  H05K1/111 ,  H05K3/0011 ,  H05K3/321 ,  H05K3/381 ,  H05K3/382 ,  H05K3/403 ,  H05K3/4076 ,  H05K2201/0257 ,  H05K2201/09472 ,  H05K2201/10659 ,  Y02P70/611

Abstract: There is provided an electric connection member having a substrate, an insulating adhesive layer provided on the substrate, and a conductive interconnect, wherein the electric connection member is provided with a recess that opens at a side of the insulating adhesive layer, the conductive interconnect is disposed in the recess, a metal nano-ink is disposed on the conductive interconnect, and all of the metal nano-ink is contained inside the recess.

公开(公告)号：US20150049443A1

公开(公告)日：2015-02-19

申请号：US13965246

申请日：2013-08-13

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg

IPC: H05K1/18

CPC classification number: H05K1/189 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/5383 ,  H01L23/5387 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/0209 ,  H05K1/0271 ,  H05K1/141 ,  H05K1/145 ,  H05K3/32 ,  H05K3/361 ,  H05K2201/05 ,  H05K2201/10378 ,  H05K2201/105 ,  H05K2201/1053 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10954 ,  H05K2201/10962 ,  H01L2924/00

Abstract: According to various embodiments, a chip arrangement may be provided, the chip arrangement may include: a first carrier; at least one chip arranged over the first carrier; a flexible structure including a wiring layer structure; and a contact structure arranged between the first carrier and the wiring layer structure, wherein the at least one chip is electrically coupled to the first carrier via the wiring layer structure and the contact structure.

Abstract translation: 根据各种实施例，可以提供芯片布置，芯片布置可以包括：第一载体; 布置在所述第一载体上的至少一个芯片; 包括布线层结构的柔性结构; 以及布置在所述第一载体和所述布线层结构之间的接触结构，其中所述至少一个芯片经由所述布线层结构和所述接触结构电耦合到所述第一载体。