公开(公告)号：US20180315820A1

公开(公告)日：2018-11-01

申请号：US15965478

申请日：2018-04-27

申请人： GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF THE NAVY

发明人： Francis J. Kub ,  Travis J. Anderson ,  Marko J. Tadjer ,  Andrew D. Koehler ,  Karl D. Hobart

IPC分类号： H01L29/267 ,  H01L29/24 ,  H01L29/861 ,  H01L29/80 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/267 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/1602 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/242 ,  H01L29/66666 ,  H01L29/66916 ,  H01L29/66924 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/802 ,  H01L29/861 ,  H01L29/8611

摘要： Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.

公开(公告)号：US20180308956A1

公开(公告)日：2018-10-25

申请号：US16017795

申请日：2018-06-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu ,  Wei-Ting Chen

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/762 ,  H01L21/311 ,  H01L27/092 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

公开(公告)号：US10083879B2

公开(公告)日：2018-09-25

申请号：US15341943

申请日：2016-11-02

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Deyuan Xiao

IPC分类号： H01L21/84 ,  H01L21/02 ,  H01L21/311 ,  H01L27/12 ,  H01L29/06 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L21/84 ,  H01L21/02236 ,  H01L21/31105 ,  H01L21/823807 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

摘要： A method for fabricating a semiconductor nanowire device includes forming a base including a plurality of PMOS regions, forming a plurality of first openings in the base of the PMOS regions, forming a plurality of first epitaxial wires by filling the first openings with a germanium-containing material, and forming a plurality of second openings in the base by etching a portion of the base under each first epitaxial wire. Each first epitaxial wire is connected to both sidewalls of a corresponding second opening and is hung above a bottom surface of the corresponding second opening. The method also includes performing a thermal oxidation treatment process on the plurality of first epitaxial wires to form an oxide layer on each first epitaxial wire, forming a plurality of first nanowires by removing the oxide layer from each first epitaxial wire, and forming a first wrap-gate structure to surround each first nanowire.

公开(公告)号：US10079313B2

公开(公告)日：2018-09-18

申请号：US15237107

申请日：2016-08-15

申请人： Samsung Electronics Co., Ltd. ,  Research & Business Foundation, SUNGKYUNKWAN UNIVERSITY

发明人： Kiyoung Lee ,  Jinseong Heo ,  Woojong Yu ,  Yongseon Shin

IPC分类号： H01L29/786 ,  H01L29/16 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66 ,  H01L21/04 ,  H01L21/02

CPC分类号： H01L29/78696 ,  H01L21/02527 ,  H01L21/02565 ,  H01L21/042 ,  H01L29/1606 ,  H01L29/247 ,  H01L29/267 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78693

摘要： A graphene electronic device includes a gate insulating layer on a conductive substrate, a channel layer on the gate insulating layer, and a source electrode on one end of the channel layer and a drain electrode on another end of the channel layer. The channel layer includes a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, and the graphene layer includes a plurality of graphene islands spaced apart from each other.

公开(公告)号：US10079279B2

公开(公告)日：2018-09-18

申请号：US15273951

申请日：2016-09-23

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Hualong Song

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/165 ,  H01L21/311 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24 ,  H01L29/267 ,  H01L29/45

CPC分类号： H01L29/0653 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02636 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76224 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/45 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.

公开(公告)号：US10074536B2

公开(公告)日：2018-09-11

申请号：US14506091

申请日：2014-10-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Anthony J. Lochtefeld

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/8258 ,  H01L29/165 ,  H01L29/06 ,  H01L29/267 ,  H01L29/66

CPC分类号： H01L21/02488 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/2018 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795

摘要： Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.

公开(公告)号：US20180254346A1

公开(公告)日：2018-09-06

申请号：US15974227

申请日：2018-05-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chun Hsiung TSAI ,  Kei-Wei CHEN

IPC分类号： H01L29/78 ,  H01L21/306 ,  H01L21/265 ,  H01L29/165 ,  H01L29/267

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/306 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.

公开(公告)号：US10050117B2

公开(公告)日：2018-08-14

申请号：US15645463

申请日：2017-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L29/10 ,  H01L29/20 ,  H01L29/267 ,  H01L29/417 ,  H01L29/43

摘要： A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US20180204953A1

公开(公告)日：2018-07-19

申请号：US15843766

申请日：2017-12-15

申请人： The Board of Trustees of the University of Illinois

发明人： Wenjuan Zhu ,  Shang-Chun Lu ,  Mohamed Mohamed

IPC分类号： H01L29/786 ,  H01L29/24 ,  H01L29/267 ,  H01L29/15 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/78642 ,  H01L21/02521 ,  H01L21/02568 ,  H01L29/155 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66969 ,  H01L29/7391 ,  H01L29/78648

摘要： The present disclosure provides vertical hetero- and homo-junction tunnel FET (TFET) based on multi-layer black phosphorus (BP) and transition metal dichalcogenides.

公开(公告)号：US10014374B2

公开(公告)日：2018-07-03

申请号：US15026271

申请日：2013-12-18

申请人： Intel Corporation

发明人： Kimin Jun ,  Patrick Morrow

IPC分类号： H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L21/762

CPC分类号： H01L29/1054 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/8258 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L29/78

摘要： In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.