公开(公告)号：US20180006140A1

公开(公告)日：2018-01-04

申请号：US15196335

申请日：2016-06-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jody Fronheiser ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Balasubramanian Pranatharthiharan ,  Mark Raymond ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/285 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L21/76895 ,  H01L21/02068 ,  H01L21/285 ,  H01L21/28525 ,  H01L21/76814 ,  H01L21/76831 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/785

Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.

公开(公告)号：US09853117B2

公开(公告)日：2017-12-26

申请号：US15342396

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20170288030A1

公开(公告)日：2017-10-05

申请号：US15353352

申请日：2016-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/41741 ,  H01L21/02266 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.

公开(公告)号：US20170287837A1

公开(公告)日：2017-10-05

申请号：US15623691

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L23/535 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L23/535 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/285 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

公开(公告)号：US09773881B2

公开(公告)日：2017-09-26

申请号：US15233315

申请日：2016-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8232 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

公开(公告)号：US20170250262A1

公开(公告)日：2017-08-31

申请号：US15594757

申请日：2017-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

公开(公告)号：US09698230B2

公开(公告)日：2017-07-04

申请号：US15283951

申请日：2016-10-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/70 ,  H01L29/417 ,  H01L29/08 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

公开(公告)号：US09685537B1

公开(公告)日：2017-06-20

申请号：US15280521

申请日：2016-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Tenko Yamashita ,  Kangguo Cheng ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/41 ,  H01L21/336 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/31051 ,  H01L21/31144 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7827 ,  H01L2029/7858

Abstract: A method of fabricating a vertical transistor is provided, the method including providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate, an impurity layer of n-type or p-type over the semiconductor substrate, a first hard mask layer over the semiconductor layer, a first dielectric layer over the first hard mask layer, a second hard mask layer over the first dielectric layer, a second dielectric layer over the second hard mask layer and a protective layer over the second dielectric layer. The method further includes patterning the second dielectric layer and protective layer, the patterning forming an opening therein, forming a wrap-around spacer on an inner sidewall of the opening, the forming leaving a smaller opening, forming a vertical channel, and setting a gate length of a wrap-around gate by removing an outer portion of the structure.

公开(公告)号：US20170154883A1

公开(公告)日：2017-06-01

申请号：US15181676

申请日：2016-06-14

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/06 ,  H01L29/93 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0733 ,  H01L29/1083 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/93

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

公开(公告)号：US20170154821A1

公开(公告)日：2017-06-01

申请号：US15291750

申请日：2016-10-12

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L29/93

CPC classification number: H01L27/0629 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0733 ,  H01L29/1083 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/93

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.