公开(公告)号：US07724475B2

公开(公告)日：2010-05-25

申请号：US11346814

申请日：2006-02-03

Applicant: Nobumasa Nishiyama

Inventor： Nobumasa Nishiyama

IPC: H05K3/36 ,  G11B5/48 ,  G11B21/16

CPC classification number: G11B5/486 ,  G11B5/484 ,  H05K1/056 ,  H05K1/111 ,  H05K2201/0792 ,  H05K2201/0969 ,  Y02P70/611 ,  Y10T29/49126

Abstract: Embodiments of the present invention provide a conductive member, in which electric characteristics can be improved by matching impedance all the way from a conductive wire to a pad. In one embodiment, a conductive member comprises: a back side metal layer; an insulating layer formed on the back side metal layer; a conductive wire formed on the insulating layer; and a pad formed on the insulating layer and electrically connected to the conductive wire; at least one opening and at least one supporting structure being formed at a position corresponding to the pad on the back side metal layer.

Abstract translation: 本发明的实施例提供一种导电构件，其中可以通过将阻抗从导线与衬垫相匹配来改善电特性。 在一个实施例中，导电构件包括：背面金属层; 形成在背面金属层上的绝缘层; 形成在所述绝缘层上的导线; 以及形成在绝缘层上并与导线电连接的焊盘; 至少一个开口和至少一个支撑结构形成在与背面金属层上的垫对应的位置处。

公开(公告)号：US20100071948A1

公开(公告)日：2010-03-25

申请号：US12250497

申请日：2008-10-13

Applicant: YI-KUANG WEI

Inventor： YI-KUANG WEI

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K1/0268 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/11 ,  H05K2201/0792 ,  H05K2201/0969 ,  Y10T29/49124

Abstract: A printed circuit board includes a signal layer, an insulation layer, and a reference layer. A transmission line is located on the signal layer. A test point is located on the transmission line. A hole is defined in the reference layer and under the test point. The signal layer, the insulation layer, and the reference layer are configured in a cascading order. Wherein an arrangement of the signal layer in relation to the reference layer comprising the hole reduces a capacitance effect caused by the test point. A method of manufacturing the printed circuit board is provided.

Abstract translation: 印刷电路板包括信号层，绝缘层和参考层。 传输线位于信号层上。 测试点位于传输线上。 在参考层和测试点下面定义一个孔。 信号层，绝缘层和参考层以级联顺序配置。 其中信号层相对于包括孔的参考层的布置减小了由测试点引起的电容效应。 提供一种制造印刷电路板的方法。

公开(公告)号：US07667980B2

公开(公告)日：2010-02-23

申请号：US11539990

申请日：2006-10-10

Applicant: Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel, Jr. ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

Inventor： Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel, Jr. ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

IPC: H05K7/00

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/09318 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/1003

Abstract: Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Abstract translation: 公开了用于对抗信号失真的印刷电路板，其包括：在发射器和接收器之间的印刷电路板上的导电路径，由连接在一起的迹线和通孔组成的导电通路，用于将信号从发射器传导到接收器; 在印刷电路板上的寄生元件，寄生元件具有扭曲信号的寄生效应; 以及一个或多个无源元件安装在导电路径附近而不连接到导电路径，无源元件具有校正效果，以减少由信号引起的寄生效应的失真。

公开(公告)号：US07564694B2

公开(公告)日：2009-07-21

申请号：US11313333

申请日：2005-12-21

Applicant: Xingjian Cai ,  Xiao-Ming Gao ,  Qing-Iun Chen

Inventor： Xingjian Cai ,  Xiao-Ming Gao ,  Qing-Iun Chen

IPC: H05K1/18

CPC classification number: H05K7/1458 ,  H05K1/0215 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/025 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/0792 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10196

Abstract: An apparatus comprising a printed circuit board having a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels; a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel; and an impedance matching terminal electrically coupled to the stub and to a ground. A process comprising providing a printed circuit board including a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels, and a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel and being designed to receive a signal from a component attached to the printed circuit board; and coupling an impedance matching terminal to the stub and to a ground.

Abstract translation: 一种装置，包括具有前侧和后侧的印刷电路板，并且其中具有多个导电层，每个导电层包括一个或多个信号通道; 从前侧延伸到后侧的短截线，短截线电耦合到至少一个信号通道; 以及电阻耦合到短截线和接地的阻抗匹配端子。 一种包括提供包括前侧和后侧的印刷电路板的工艺，其中包括多个导电层，每个导电层包括一个或多个信号通道，以及从前侧向后侧延伸的短截线 短截线被电耦合到至少一个信号通道并且被设计成从附接到印刷电路板的部件接收信号; 并将阻抗匹配端子耦合到短截线和接地。

公开(公告)号：US20090073634A1

公开(公告)日：2009-03-19

申请号：US12155583

申请日：2008-06-06

Applicant: Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

Inventor： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC: H01G4/005

CPC classification number: H01L23/50 ,  H01G4/35 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad. The first via is disposed adjacent to the third pad relative to a central line of the first pad, the second via is disposed adjacent to the third pad relative to a central line of the second pad, one or more of the third vias are disposed adjacent to the first via relative to a central line of the third pad, and the rest of the third vias are disposed adjacent to the second via relative to the central line of the third pad.

Abstract translation: 一种电路板，包括：具有用于安装具有第一极性的第一和第二外部电极和第二极性的第三外部电极的垂直多层片状电容器的安装区域的基板; 布置在安装区域上的第一至第三焊盘，第一和第二焊盘具有第一极性并且在安装区域上彼此分开设置，第三焊盘具有第二极性并且设置在第一焊盘和第二焊盘之间以连接到 第三外部电极; 至少一个第一通孔，其形成在所述基板中并连接到所述第一焊盘; 至少一个第二通孔，形成在所述衬底中并连接到所述第二衬垫; 以及形成在基板中并连接到第三焊盘的多个第三通孔。 第一通孔相对于第一焊盘的中心线设置成与第三焊盘相邻，第二通孔相对于第二焊盘的中心线设置为与第三焊盘相邻，第一通孔中的一个或多个邻近 相对于第三焊盘的中心线移动到第一通孔，并且第三通孔的其余部分相对于第三焊盘的中心线设置成与第二通孔相邻。

公开(公告)号：US07474539B2

公开(公告)日：2009-01-06

申请号：US11105141

申请日：2005-04-11

Applicant: Chung-Chi Huang ,  Richard Kunze ,  Beom-Taek Lee

Inventor： Chung-Chi Huang ,  Richard Kunze ,  Beom-Taek Lee

IPC: H05K7/00

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0233 ,  H05K1/165 ,  H05K2201/0792 ,  H05K2201/0949 ,  H05K2201/1003 ,  H05K2201/10325 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A component having an inductor to at least partially compensate for a capacitance in a circuit of the component, is described herein.

Abstract translation: 这里描述了具有至少部分地补偿组件的电路中的电容的电感器的部件。

公开(公告)号：US07470863B2

公开(公告)日：2008-12-30

申请号：US11338402

申请日：2006-01-24

Applicant: Hanyi Ding ,  Brian P. Welch

Inventor： Hanyi Ding ,  Brian P. Welch

IPC: H05K1/16

CPC classification number: H05K1/024 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/0792 ,  H05K2201/09581 ,  H01L2924/00

Abstract: A microelectronic device and method of making the microelectronic device is provided. A dielectric substrate having first and second surfaces is provided. A first component, located in the dielectric substrate between the first and second surfaces of the dielectric substrate is formed. The first component includes a first interface and a second interface. A second component located in the dielectric substrate and spaced relative to the first component is formed, and a first low permittivity material is formed having a predetermined thickness and a first and second surface, the first surface of the low permittivity material is adjacent to or in contact with a first portion of the first interface of the first component. The first low permittivity material substantially reduces capacitive parasitics of the first component, resulting in a substantially higher characteristic impedance of the first component during operation of the microelectronic device.

Abstract translation: 提供微电子器件和制造微电子器件的方法。 提供具有第一和第二表面的电介质基片。 形成位于电介质基板之间的电介质基板的第一和第二表面之间的第一部件。 第一组件包括第一接口和第二接口。 形成位于电介质基板中并相对于第一部件间隔开的第二部件，并且形成具有预定厚度的第一低介电常数材料和第一和第二表面，低介电常数材料的第一表面邻近或介于 与第一部件的第一界面的第一部分接触。 第一低介电常数材料显着地减小了第一部件的电容寄生效应，导致在微电子器件工作期间第一部件的特征阻抗基本上更高。

公开(公告)号：US20080239622A1

公开(公告)日：2008-10-02

申请号：US11950381

申请日：2007-12-04

Applicant: Chien-Min HSU ,  Shih-Hsien WU ,  Min-Lin LEE ,  Shinn-Juh LAI

Inventor： Chien-Min HSU ,  Shih-Hsien WU ,  Min-Lin LEE ,  Shinn-Juh LAI

IPC: H01G4/236 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.

Abstract translation: 本发明涉及一种用于降低层叠电容器的等效串联电感（ESL）的布线结构。 层叠电容器包括多个导电层，沿层叠电容器的厚度方向延伸的电力通孔，并且从顶部导电层延伸至底部导电层，沿着层叠电容器的厚度方向延伸的接地通孔 并布置成从顶部导电层延伸到底部导电层。 导电层包括一组第一导电层和一组第二导电层。 电源通孔电耦合到第一导电层，并且接地通孔电耦合到第二导电层。 层叠电容器还包括电源通孔和接地通孔之间的补充通路。 补充通孔的长度要短于电源通孔和接地通孔。 辅助通孔电耦合到第一导电层和第二导电层之一。

公开(公告)号：US20080073796A1

公开(公告)日：2008-03-27

申请号：US11535700

申请日：2006-09-27

Applicant: Paul M. Harvey ,  Kazushige Kawasaki ,  Gen Yamada

Inventor： Paul M. Harvey ,  Kazushige Kawasaki ,  Gen Yamada

IPC: H01L23/48

CPC classification number: H05K1/116 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.

Abstract translation: 提供了用于多层互连基板中的高速信号的电学优化和结构保护的微通孔结构。 通孔结构消除了与参考平面的接触的重叠，从而减小了通孔电容，从而减小了通孔结构中的通路阻抗失配。 结果，通孔结构被电学优化。 通孔结构还包括一个或多个浮动支撑构件，该浮动支撑构件在通孔和参考平面之间的通孔间隙区域内靠近通孔放置。 浮动支撑构件在它们不与通孔或参考平面电接触的意义上是“浮动的”。 因此，它们不是用于信号传播的目的，而是仅用于结构支持。 浮动支撑构件可以通过一个或多个微孔结构彼此连接。

公开(公告)号：US07305760B2

公开(公告)日：2007-12-11

申请号：US10924629

申请日：2004-08-24

Applicant: Abeye Teshome ,  Lan Zhang

Inventor： Abeye Teshome ,  Lan Zhang

IPC: H01R43/00 ,  H05K13/00

CPC classification number: H05K1/0216 ,  H05K1/0263 ,  H05K1/112 ,  H05K1/162 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/49169

Abstract: Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.

Abstract translation: 通过电路板提供给信息处理系统电子元件的功率具有通过配置与电子元件的连接以补偿寄生电容的组件封装电感寄生效应。 例如，将处理器连接到电路板的电源和接地平面的电源和接地通孔对准以产生期望的寄生电容，其减少与信号补偿，功率输送和高速去耦合有关的寄生电感的影响。 期望的分布电容通过改变与功率通孔的等效线电荷相关联的半径，与电源和接地通孔之间的线路电荷相关联的距离以及通孔筒长度来建模。