公开(公告)号：US20170342556A1

公开(公告)日：2017-11-30

申请号：US15590063

申请日：2017-05-09

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： KATHRINE CROOK ,  MARK CARRUTHERS ,  ANDREW PRICE

IPC: C23C16/44 ,  B08B7/00 ,  H01J37/32

CPC classification number: C23C16/4405 ,  B08B7/0035 ,  C23C16/452 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32862 ,  H01J37/32963 ,  H01J2237/335

Abstract: A method of cleaning a chamber of a plasma processing device with radicals includes creating a plasma within a remote plasma source which is separated from the chamber, the plasma including radicals and ions, cleaning the chamber by allowing radicals to enter the chamber from the remote plasma source while preventing the majority of the ions created in the remote plasma source from entering the chamber, detecting a DC bias developed on a component of the chamber during cleaning; and using the detected DC bias to determine an end-point of the cleaning and, on determination of the end-point, to stop the cleaning.

公开(公告)号：US20170117166A1

公开(公告)日：2017-04-27

申请号：US15293153

申请日：2016-10-13

Applicant: SPTS Technologies Limited

Inventor： Gautham Ragunathan ,  David Tossell ,  Oliver Ansell

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/67069 ,  H01J37/32623 ,  H01J37/32715 ,  H01L21/3065 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6836 ,  H01L21/68721 ,  H01L21/68778 ,  H01L21/68785 ,  H01L21/78 ,  H01L2221/68327

Abstract: An apparatus is for plasma dicing a semiconductor substrate of the type forming part of a workpiece, the workpiece further including a carrier sheet on a frame member, where the carrier sheet carries the semiconductor substrate. The apparatus includes a chamber, a plasma production device configured to produce a plasma within the chamber suitable for dicing the semiconductor substrate, a workpiece support located in the chamber for supporting the workpiece through contact with the carrier sheet, and a frame cover element configured to, in use, contact the frame member thereby clamping the carrier sheet against an auxiliary element disposed in the chamber.

公开(公告)号：US09601341B2

公开(公告)日：2017-03-21

申请号：US14577442

申请日：2014-12-19

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Huma Ashraf

IPC: H01L21/76 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/308 ,  H01L21/02 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/30655 ,  H01L21/0212 ,  H01L21/0334 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/76816 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of etching a feature in a substrate includes forming a mask structure over the substrate, the mask structure defining at least one re-entrant opening, etching the substrate through the opening to form the feature using a cyclic etch and deposition process, and removing the mask.

公开(公告)号：US20160265108A1

公开(公告)日：2016-09-15

申请号：US15064631

申请日：2016-03-09

Applicant: SPTS Technologies Limited

Inventor： DANIEL T. ARCHARD ,  STEPHEN R. BURGESS ,  MARK I. CARRUTHERS ,  ANDREW PRICE ,  KEITH E. BUCHANAN ,  KATHERINE CROOK

IPC: C23C16/455 ,  C23C16/513

CPC classification number: C23C16/455 ,  C23C16/513 ,  H01J37/32633 ,  H01J37/32834

Abstract: A plasma-enhanced chemical vapour deposition (PE-CVD) apparatus includes a chamber including a circumferential pumping channel, a substrate support disposed within the chamber, one or more gas inlets for introducing gas into the chamber, a plasma production device for producing a plasma in the chamber, and an upper and a lower element positioned in the chamber. The upper element is spaced apart from the substrate support to confine the plasma and to define a first circumferential pumping gap, and the upper element acts as a radially inward wall of the circumferential pumping channel. The upper and lower elements are radially spaced apart to define a second circumferential pumping gap which acts as an entrance to the circumferential pumping channel, in which the second circumferential pumping gap is wider than the first circumferential pumping gap.

Abstract translation: 等离子体增强化学气相沉积（PE-CVD）装置包括：腔室，包括圆周泵浦通道，设置在腔室内的衬底支撑件，用于将气体引入腔室的一个或多个气体入口;用于产生等离子体的等离子体生产装置 在腔室中，以及位于腔室中的上部和下部元件。 上部元件与衬底支撑件间隔开以限制等离子体并且限定第一周向泵送间隙，并且上部元件用作圆周泵送通道的径向向内的壁。 上部和下部元件径向间隔开以限定作为周向泵送通道入口的第二圆周泵送间隙，其中第二圆周泵送间隙比第一圆周泵送间隙宽。

公开(公告)号：US20160126129A1

公开(公告)日：2016-05-05

申请号：US14925715

申请日：2015-10-28

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： ANTHONY BARKER ,  HUMA ASHRAF ,  BRIAN KIERNAN

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/68728 ,  H01J37/32082 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/68721

Abstract: A clamp assembly is for clamping an outer peripheral portion of a substrate to a support in a plasma processing chamber. An RF bias power is applied to the support during the plasma processing of the substrate. The clamp assembly includes an outer clamp member, and an inner clamp member which is received by the outer clamp member, the inner clamp member defining an aperture which exposes the substrate to the plasma processing. The outer clamp member has an inner portion terminating in an inner edge, wherein the inner portion is spaced apart from the inner clamp member.

Abstract translation: 夹具组件用于将衬底的外周部分夹持到等离子体处理室中的支撑件上。 在衬底的等离子体处理期间将RF偏置功率施加到支撑件。 夹紧组件包括外部夹紧构件和内部夹紧构件，其由外部夹紧构件接收，内部夹具构件限定将衬底暴露于等离子体处理的孔。 外部夹紧构件具有终止于内部边缘的内部部分，其中内部部分与内部夹紧构件间隔开。

公开(公告)号：US20150125375A1

公开(公告)日：2015-05-07

申请号：US14532098

申请日：2014-11-04

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： YUN ZHOU ,  RHONDA HYNDMAN ,  STEPHEN R. BURGESS

IPC: C23C14/00 ,  C23C14/35 ,  C01B33/12 ,  C23C14/34

CPC classification number: C23C14/0036 ,  C01B33/12 ,  C23C14/10 ,  C23C14/3485 ,  C23C14/35

Abstract: According to the invention there is a method of depositing SiO2 onto a substrate by pulsed DC reactive sputtering which uses a sputtering gas mixture consisting essentially of oxygen and krypton.

Abstract translation: 根据本发明，通过使用基本上由氧和氪组成的溅射气体混合物的脉冲DC反应溅射，将SiO 2沉积到衬底上的方法。

公开(公告)号：US20150075973A1

公开(公告)日：2015-03-19

申请号：US14483926

申请日：2014-09-11

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： ALEX THEODOSIOU ,  STEVE BURGESS

IPC: H01L21/02 ,  H01L21/67

Abstract: The invention relates to a method of pre-cleaning a semiconductor structure and to associated modular semiconductor process tools. The method includes the steps of: (i) providing a semiconductor structure having an exposed dielectric layer of an organic dielectric material, wherein the dielectric layer has one or more features formed therein which expose one or more electrically conductive structures to be pre-cleaned, in which the electrically conductive structures each include a metal layer, optionally with a barrier layer formed thereon, and the surface area of the exposed dielectric layer is greater than the surface area of the electrically conductive structures exposed by the dielectric layer; and (ii) pre-cleaning the semiconductor structure by performing an Ar/H2 sputter etch to remove material from the exposed electrically conductive structures and to remove organic dielectric material from the exposed dielectric layer.

Abstract translation: 本发明涉及一种预清洁半导体结构和相关的模块化半导体工艺工具的方法。 该方法包括以下步骤：（i）提供具有有机介电材料的暴露电介质层的半导体结构，其中介电层具有形成在其中的一个或多个特征，其暴露要预清洁的一个或多个导电结构， 其中导电结构各自包括金属层，任选地在其上形成阻挡层，并且暴露的电介质层的表面积大于由电介质层暴露的导电结构的表面积; 和（ii）通过执行Ar / H 2溅射蚀刻来预先清洁半导体结构，以从暴露的导电结构去除材料并从暴露的介电层去除有机电介质材料。

公开(公告)号：US08709268B2

公开(公告)日：2014-04-29

申请号：US13674482

申请日：2012-11-12

Applicant: SPTS Technologies Limited

Inventor： Oliver James Ansell

IPC: G01L21/30 ,  G01R31/00

CPC classification number: H01J37/32963 ,  B81C99/0065 ,  B81C2201/0135 ,  B81C2201/0142 ,  H01J37/32972 ,  H01L22/26

Abstract: A method of etching the whole width of a substrate to expose buried features is disclosed. The method includes etching a face of a substrate across its width to achieve substantially uniform removal of material; illuminating the etched face during the etch process; applying edge detection techniques to light reflected or scattered from the face to detect the appearances of buried features; and modifying the etch in response to the detection of the buried feature. An etching apparatus for etching substrate across its width to expose buried is also disclosed.

Abstract translation: 公开了一种蚀刻衬底的整个宽度以暴露掩埋特征的方法。 该方法包括在其宽度上蚀刻衬底的表面以实现材料的基本上均匀的去除; 在蚀刻过程中照射蚀刻的面; 将边缘检测技术应用于从脸部反射或散射的光，以检测埋藏特征的外观; 以及响应于所述掩埋特征的检测来修改所述蚀刻。 还公开了一种用于蚀刻衬底跨越其宽度以暴露掩埋的蚀刻装置。

公开(公告)号：US20140113439A1

公开(公告)日：2014-04-24

申请号：US14056529

申请日：2013-10-17

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： JASH PATEL ,  YUFEI LIU

IPC: H01L21/02

CPC classification number: H01L21/02592 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658

Abstract: A method is for depositing in a chamber an amorphous silicon layer on a surface of a semiconducting or insulating substrate. In the method, the surface is pretreated with a NH3 plasma prior to deposition of the amorphous silicon layer.

Abstract translation: 一种用于在半导体或绝缘衬底的表面上在室中沉积非晶硅层的方法。 在该方法中，在沉积非晶硅层之前，用NH 3等离子体预处理表面。

公开(公告)号：US20140097153A1

公开(公告)日：2014-04-10

申请号：US14043818

申请日：2013-10-01

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Huma ASHRAF ,  Anthony BARKER

IPC: C23F1/12

CPC classification number: C23F1/12 ,  H01J37/32449 ,  H01L21/3065 ,  H01L21/3081

Abstract: a method of plasma etching a silicon carbide workpiece includes forming a mask on a surface of the silicon carbide workpiece, performing an initial plasma etch on the masked surface using a first set of process conditions, wherein the plasma is produced using an etchant gas mixture which includes i) oxygen and ii) at least one fluorine rich gas which is present in the etchant gas mixture at a volume ratio of less than 50%, and subsequently performing a bulk plasma etch process using a second set of process conditions which differ from the first set of process conditions.

Abstract translation: 等离子体蚀刻碳化硅工件的方法包括在碳化硅工件的表面上形成掩模，使用第一组工艺条件在掩模表面上进行初始等离子体蚀刻，其中使用蚀刻剂气体混合物 包括i）氧和ii）以等于50％的体积比存在于蚀刻剂气体混合物中的至少一种富含氟的气体，并且随后使用与第二组工艺条件不同的第二组工艺条件进行本体等离子体蚀刻工艺 第一套工艺条件。