公开(公告)号：US06746947B2

公开(公告)日：2004-06-08

申请号：US10254277

申请日：2002-09-25

申请人： Timothy H. Daubenspeck ,  Daniel C. Edelstein ,  Robert M. Geffken ,  William T. Motsiff ,  Anthony K. Stamper ,  Steven H. Voldman

发明人： Timothy H. Daubenspeck ,  Daniel C. Edelstein ,  Robert M. Geffken ,  William T. Motsiff ,  Anthony K. Stamper ,  Steven H. Voldman

IPC分类号： H01L2144

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/76843 ,  H01L23/5258 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.

摘要翻译： 公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。 使用镶嵌工艺完成制作。 金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面 在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。 金属结构可用作耐腐蚀保险丝。 金属结构也可以用作电阻元件。 高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。 电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。 电阻器结构可以形成在电介质槽的壁上。 该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。 电阻可以与MOSFET或其他结构串联。

公开(公告)号：US06455914B2

公开(公告)日：2002-09-24

申请号：US09842545

申请日：2001-04-26

申请人： Dennis P. Bouldin ,  Timothy H. Daubenspeck ,  William T. Motsiff

发明人： Dennis P. Bouldin ,  Timothy H. Daubenspeck ,  William T. Motsiff

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines. This applies to wiring layers formed from “high” melting temperature metals and those defined using a damascene process. For example, copper back end of line (Cu BEOL) damascene wiring, as used with CMOS can use the invention. The technique achieves high yield fusing for technologies that use thick wiring layers. The structure separates the thickness of the fuse segment from the remainder of the wiring line. The structure can be used with very thick, e.g., >1.2 &mgr; wiring and very thin, e.g.,

摘要翻译： 公开了一种制造金属化熔丝线的结构和方法。 该结构可以形成在半导体衬底上，包括形成在衬底上的绝缘体结构，绝缘体结构具有上层和下层，上部比下部更薄，绝缘体结构具有多个不同深度的开口 以及镶嵌在绝缘体结构中的金属结构，具有第一和第二部分的金属结构和在其之间的第三部分比第一和第二部分具有更大的阻力，第三部分的厚度基本上类似于 上层绝缘体结构。 上层包括氮化物，下层包括氧化物，金属结构包括铜。 熔丝结构允许在厚金属线段内形成“易于激光删除”的薄金属保险丝。 这适用于由“高”熔融金属形成的布线层和使用镶嵌工艺定义的布线层。 例如，与CMOS一起使用的铜后端（Cu BEOL）镶嵌布线可以使用本发明。 该技术实现了使用厚布线层的技术的高产率熔合。 该结构将熔丝段的厚度与布线的其余部分分开。 该结构可以使用非常厚的例如>1.2μm的布线和非常薄的例如<0.5μ的保险丝。

公开(公告)号：US5596226A

公开(公告)日：1997-01-21

申请号：US301290

申请日：1994-09-06

申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Timothy H. Daubenspeck ,  Wayne J. Howell

发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Timothy H. Daubenspeck ,  Wayne J. Howell

IPC分类号： H01L25/18 ,  H01L21/02 ,  H01L21/301 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L27/00 ,  H01L27/04 ,  H01L23/48

CPC分类号： H01L25/50 ,  H01L24/24 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/14

摘要： A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.

摘要翻译： 一种制造方法，包括半导体芯片切痕工艺以及由此形成的半导体芯片和电子模块。 制造方法包括提供包括多个集成电路芯片的晶片，其中它们之间具有切口区域。 芯片金属化存在于切口区域内。 使用光刻工艺来保护仅暴露切口区域的晶片。 接下来，蚀刻晶片，从切口区域清除芯片金属化。 然后切割晶片，并且将芯片堆叠以形成单片电子模块。 处理电子模块的侧表面以暴露延伸到其上的转移金属，从而便于与电子模块内的芯片的电连接。 阐述了制造方法的具体细节，所得到的集成电路芯片和单片电子模块。

公开(公告)号：US5219788A

公开(公告)日：1993-06-15

申请号：US661561

申请日：1991-02-25

申请人： John R. Abernathey ,  Timothy H. Daubenspeck ,  Stephen E. Luce ,  Denis J. Poley ,  Rosemary A. Previti-Kelly ,  Gary P. Viens ,  Jung H. Yoon

发明人： John R. Abernathey ,  Timothy H. Daubenspeck ,  Stephen E. Luce ,  Denis J. Poley ,  Rosemary A. Previti-Kelly ,  Gary P. Viens ,  Jung H. Yoon

IPC分类号： G03F7/11 ,  G03F7/09 ,  G03F7/36 ,  H01L21/027

CPC分类号： G03F7/091 ,  Y10S438/902 ,  Y10S438/95 ,  Y10S438/952

摘要： A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO.sub.2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

公开(公告)号：US08796133B2

公开(公告)日：2014-08-05

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US08765593B2

公开(公告)日：2014-07-01

申请号：US13569674

申请日：2012-08-08

申请人： Stephen P. Ayotte ,  Timothy H. Daubenspeck ,  David J. Hill ,  Glen E. Richard ,  Timothy M. Sullivan

发明人： Stephen P. Ayotte ,  Timothy H. Daubenspeck ,  David J. Hill ,  Glen E. Richard ,  Timothy M. Sullivan

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11614 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13684 ,  H01L2224/13687 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14151 ,  H01L2224/1416 ,  H01L2224/14177 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Aspects of the present invention relate to a controlled collapse chip connection (C4) structures. Various embodiments include a method of forming a controlled collapse chip connection (C4) structure. The method can include: providing a precursor structure including: a substrate, a dielectric over the substrate, the dielectric including a plurality of trenches exposing a portion of the substrate, and a metal layer over the dielectric and the portion of the substrate in each of the plurality of trenches, forming a resist layer over the metal layer, forming a rigid liner over a surface of the resist layer and the metal layer, and forming solder over the rigid liner between portions of the resist layer.

摘要翻译： 本发明的方面涉及一种受控的崩溃芯片连接（C4）结构。 各种实施例包括形成受控崩溃芯片连接（C4）结构的方法。 该方法可以包括：提供前体结构，其包括：衬底，在衬底上的电介质，电介质包括暴露衬底的一部分的多个沟槽，以及覆盖在电介质上的金属层和衬底的每一个中的金属层 所述多个沟槽在所述金属层上形成抗蚀剂层，在所述抗蚀剂层和所述金属层的表面上形成刚性衬垫，以及在所述抗蚀剂层的部分之间的所述刚性衬垫上形成焊料。

公开(公告)号：US20140021622A1

公开(公告)日：2014-01-23

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US08446006B2

公开(公告)日：2013-05-21

申请号：US12640752

申请日：2009-12-17

申请人： Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Gary LaFontant ,  Ian D. Melville ,  Ekta Misra ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Robin A. Susko ,  Thomas A. Wassick ,  Xiaojin Wei ,  Steven L. Wright

发明人： Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Gary LaFontant ,  Ian D. Melville ,  Ekta Misra ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Robin A. Susko ,  Thomas A. Wassick ,  Xiaojin Wei ,  Steven L. Wright

IPC分类号： H01L23/498 ,  H01L21/3205

CPC分类号： H01L23/49816 ,  H01L21/76804 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05094 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.

摘要翻译： 公开了减少焊球中的最大电流密度的结构和方法。 一种方法包括在最后的布线层中形成接触焊盘，并且形成从接触焊盘的侧边缘延伸到多个通孔中的多个通孔的接触焊盘的多个导线。 多个导线中的每一根具有基本上相同的电阻。

公开(公告)号：US20130098176A1

公开(公告)日：2013-04-25

申请号：US13277246

申请日：2011-10-20

申请人： William E. Bernier ,  Timothy H. Daubenspeck ,  Virendra R. Jadhav ,  Valerie A. Oberson ,  David L. Questad

发明人： William E. Bernier ,  Timothy H. Daubenspeck ,  Virendra R. Jadhav ,  Valerie A. Oberson ,  David L. Questad

IPC分类号： G01N33/00

CPC分类号： H01L22/30 ,  B05D1/36 ,  G01N3/60 ,  G01N19/04 ,  G01N25/16 ,  G01N2203/0296 ,  G01N2203/0298 ,  H01L24/13 ,  H01L2224/131 ,  H01L2924/10253 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

摘要： A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.

摘要翻译： 公开了一种对称的平板层压结构，用于使测试结构中的变量最小化，以实验测量白色凸起对CTE不匹配的敏感性。 测试结构包括平板层压结构。 使用测试结构的方法包括隔离多变量芯片连接问题的原因，其由翘曲不利地影响并量化翘曲的贡献本身在多变量芯片连接问题的形成中。

公开(公告)号：US08299581B2

公开(公告)日：2012-10-30

申请号：US12796068

申请日：2010-06-08

申请人： Timothy H. Daubenspeck ,  Ekta Misra ,  Marie-Claude Paquet ,  Francis Santerre ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Ekta Misra ,  Marie-Claude Paquet ,  Francis Santerre ,  Wolfgang Sauter

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide a semiconductor chip having a passivation layer extending along a surface of a semiconductor substrate to an edge of the semiconductor substrate, and methods for their formation. One aspect of the invention provides a semiconductor chip comprising: a semiconductor substrate; a passivation layer including a photosensitive polyimide disposed along a surface of the semiconductor substrate and extending to at least one edge of the semiconductor substrate; and a channel extending through the passivation layer to the surface of the semiconductor substrate.

摘要翻译： 本发明的实施例提供了具有沿着半导体衬底的表面延伸到半导体衬底的边缘的钝化层的半导体芯片及其形成方法。 本发明的一个方面提供一种半导体芯片，包括：半导体衬底; 钝化层，包括沿半导体衬底的表面设置并延伸到半导体衬底的至少一个边缘的光敏聚酰亚胺; 以及延伸穿过钝化层到半导体衬底的表面的沟道。