公开(公告)号：US20120217610A1

公开(公告)日：2012-08-30

申请号：US13037281

申请日：2011-02-28

申请人： Peter J. Hopper ,  Peter Johnson ,  Luu Nguyen ,  Peter Smeys

发明人： Peter J. Hopper ,  Peter Johnson ,  Luu Nguyen ,  Peter Smeys

IPC分类号： H01L29/02 ,  H01L21/762

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13647 ,  H01L2224/13686 ,  H01L2224/16145 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

摘要翻译： 键合半导体结构体是以首先形成金字塔状的开口的阴半导体结构体和具有金字塔形突起的阳半导体结构体的方式形成的，然后将凸部插入到开口中，以使阳半导体结构与阴半导体 结合结构。

公开(公告)号：US20120200377A1

公开(公告)日：2012-08-09

申请号：US13020052

申请日：2011-02-03

申请人： Dok Won Lee ,  Peter Johnson ,  Aditi Dutt Chaudhuri

发明人： Dok Won Lee ,  Peter Johnson ,  Aditi Dutt Chaudhuri

IPC分类号： H01H50/44 ,  H01F7/06 ,  H01H53/06

CPC分类号： H01L29/84 ,  H01H1/0036 ,  H01H49/00 ,  H01H50/005 ,  H01H50/36 ,  H01H50/44 ,  Y10T29/49073

摘要： A micro-electromechanical systems (MEMS) relay includes a switch with a first contact region and a second contact region that are vertically separated from each other by a gap. The MEMS relay requires a small vertical movement to close the gap and therefore is mechanically robust. In addition, the MEMS relay has a small footprint and, therefore, can be formed on top of small integrated circuits.

摘要翻译： 微机电系统（MEMS）继电器包括具有通过间隙彼此垂直分离的第一接触区域和第二接触区域的开关。 MEMS继电器需要小的垂直运动来封闭间隙，因此机械稳健。 此外，MEMS继电器占地面积小，因此可以形成在小型集成电路之上。

公开(公告)号：US20120125238A1

公开(公告)日：2012-05-24

申请号：US12949715

申请日：2010-11-18

申请人： Peter Johnson ,  Rick Johnson

发明人： Peter Johnson ,  Rick Johnson

IPC分类号： B65D19/38 ,  B23P11/00

CPC分类号： B65D19/08 ,  B23P15/00 ,  B65D19/0095 ,  B65D2203/10 ,  B65D2519/00024 ,  B65D2519/00059 ,  B65D2519/00094 ,  B65D2519/00273 ,  B65D2519/00278 ,  B65D2519/00293 ,  B65D2519/00298 ,  B65D2519/00323 ,  B65D2519/00333 ,  B65D2519/00567 ,  B65D2519/00572 ,  B65D2519/00835 ,  B65D2519/00985 ,  B65D2519/0099 ,  Y10T29/49826 ,  Y10T29/49947

摘要： A weldless aluminum pallet has slats that interlock with outside and inside stringers to form the pallet without need for permanent attachment points. Grooves in the stringers receive a projection on each slat, holding the slat in place. Preferably, a single projection extends along the length of the slat body. The projection is shaped to cooperate with the groove such that the slat attaches perpendicularly to the stringers. The groove is shaped to retain the slat's projection by friction fit, creating an interlocking joint. The front and rear slats on each face may be fastened to the stringers by screws or other removable fasteners. Pure aluminum or an aluminum alloy may be used, and the material may be tempered using known tempering techniques. The preferred material is 100% recycled 6005-T6 aluminum alloy. The parts are preferably extruded but alternatively may be molded or otherwise die cast.

摘要翻译： 无焊铝托盘具有与外部和内部纵梁互锁的板条，以形成托盘，而不需要永久的连接点。 桁条中的沟槽在每条板条上收到一个投影，将板条保持在原位。 优选地，单个突起沿着板条主体的长度延伸。 凸起成形为与槽配合，使得板条垂直地附着在桁条上。 凹槽被成形为通过摩擦配合来保持板条的突出部，从而产生互锁接头。 每个表面上的前板和后板可以通过螺钉或其他可拆卸的紧固件固定在桁条上。 可以使用纯铝或铝合金，并且可以使用已知的回火技术来回火材料。 优选的材料是100％回收的6005-T6铝合金。 这些部件优选地被挤出，但是可替代地可以被模塑或以其他方式压铸。

公开(公告)号：US20110250730A1

公开(公告)日：2011-10-13

申请号：US12756097

申请日：2010-04-07

申请人： Peter J. Hopper ,  William French ,  Peter Smeys ,  Peter Johnson

发明人： Peter J. Hopper ,  William French ,  Peter Smeys ,  Peter Johnson

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.

摘要翻译： 具有大量板和微法拉范围内的电容的交叉指向的半导体电容器仅在单个光刻步骤上形成在晶片上，通过沉积与晶片间隔开的第一荫罩，每个奇数层的金属， 以及通过与晶片间隔开的第二荫罩的每个偶数金属层。

公开(公告)号：US07901984B2

公开(公告)日：2011-03-08

申请号：US12479715

申请日：2009-06-05

申请人： Peter Smeys ,  Peter Johnson ,  Peter Deane

发明人： Peter Smeys ,  Peter Johnson ,  Peter Deane

IPC分类号： H01L21/66 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/642 ,  H01L23/645 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/16 ,  H01L2221/68377 ,  H01L2223/6677 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed. The integrated circuit is electrically connected to the external package contacts at least partly through one or more of the conductive interconnect layers. Various embodiments pertain to apparatuses that are formed by performing some or all of the aforementioned operations.

摘要翻译： 描述了用于形成集成电路封装的各种装置和方法。 本发明的一个方面涉及在微系统中形成微系统和一个或多个无源器件的方法。 环氧树脂层依次沉积在衬底上以在衬底上形成多个环氧树脂平坦化层。 环氧树脂层通过旋涂沉积。 至少一些环氧树脂层在沉积之后并且在下一个环氧树脂层沉积之前被光刻图案化。 具有多个I / O接合焊盘的集成电路被放置在相关联的环氧树脂层上。 在相关联的环氧树脂层上形成至少一个导电互连层。 在至少一个环氧树脂层内形成无源部件。 无源部件经由互连层中的至少一个与集成电路电耦合。 形成多个外部封装触点。 至少部分地通过一个或多个导电互连层将集成电路电连接到外部封装触点。 各种实施例涉及通过执行上述操作中的一些或全部而形成的装置。

公开(公告)号：US07901981B2

公开(公告)日：2011-03-08

申请号：US12479707

申请日：2009-06-05

申请人： Peter Smeys ,  Peter Johnson ,  Peter Deane

发明人： Peter Smeys ,  Peter Johnson ,  Peter Deane

IPC分类号： H01L21/66 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L23/427 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/642 ,  H01L23/645 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/112 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed. The integrated circuit is electrically connected with the external package contacts at least in part through one or more of the conductive interconnect layers.

摘要翻译： 描述了用于形成集成电路微模块的各种方法。 在本发明的一个方面，环氧树脂层顺序地沉积在衬底上以在衬底上形成环氧化物的平坦化层。 使用旋涂来沉积环氧树脂层。 至少一些层在沉积之后并且在下一个环氧树脂层沉积之前被光刻图案化。 在其图案化之后并且在下一个环氧树脂层沉积之前，在至少一些图案化环氧树脂层中形成开口。 集成电路放置在一个开口内。 在集成电路放置以覆盖集成电路之后，至少一个环氧树脂层被沉积。 在相关联的环氧树脂层上形成至少一个导电互连层。 形成多个外部封装触点。 该集成电路至少部分地通过一个或多个导电互连层与外部封装触头电连接。

公开(公告)号：US07898068B2

公开(公告)日：2011-03-01

申请号：US12479709

申请日：2009-06-05

申请人： Peter Smeys ,  Peter Johnson ,  Peter Deane

发明人： Peter Smeys ,  Peter Johnson ,  Peter Deane

IPC分类号： H01L23/02 ,  H01L23/12 ,  H01L23/053 ,  H01L23/34

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/185 ,  H05K3/0058 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2224/82 ,  H01L2924/00

摘要： Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.

摘要翻译： 描述了用于改善来自集成电路微模块的散热的各种装置和方法。 本发明的一个方面涉及具有一个或多个热管的集成电路封装。 在这方面，集成电路封装包括多层固化的平坦化电介质。 电气装置嵌入到至少一个电介质层中。 至少一个导电互连层嵌入在一个或多个介电层内。 由导热材料制成的热管嵌入在至少一个相关介电层中。 热管将电气装置与集成电路封装的一个或多个外表面热耦合。 描述了用于形成集成电路封装的各种方法。

公开(公告)号：US20110025443A1

公开(公告)日：2011-02-03

申请号：US12899384

申请日：2010-10-06

申请人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

发明人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

IPC分类号： H01F5/00 ,  H01L21/02

CPC分类号： H01L23/5227 ,  C23C28/023 ,  C25D5/022 ,  C25D7/123 ,  C25D17/001 ,  H01L27/0207 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

摘要翻译： 用于直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。 该装置和方法包括制造包括多个骰子的半导体晶片，每个骰子包括电源电路和开关节点。 一旦制造晶片，则分别将多个电感器直接制造在晶片上的多个晶片上。 每个电感器通过在形成在晶片上的互连电介质层上形成多个磁芯电感器构件来制造。 然后在每个管芯上方的多个磁芯电感器部件上形成绝缘层，然后形成电感器线圈。 分别在多个电感器上形成电镀磁性层，以提高结构的磁导率和电感。

公开(公告)号：US07843056B2

公开(公告)日：2010-11-30

申请号：US12390349

申请日：2009-02-20

申请人： Peter Smeys ,  Peter Johnson ,  Peter Deane

发明人： Peter Smeys ,  Peter Johnson ,  Peter Deane

IPC分类号： H01L23/04 ,  H01L23/12 ,  H01L23/053 ,  H01L23/34

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/24227 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type. In a method aspect of the invention, the dielectric layers may be formed using a spin-on coating approach and patterned using conventional photolithographic techniques.

摘要翻译： 在一个方面，描述了由固化的，平坦化的可光致成像电介质的多个紧邻的堆叠层组成的集成电路封装。 在一对相邻的电介质层之间提供至少一个互连层。 集成电路位于一个或多个介电层内，使得至少一个电介质层在集成电路的有源表面上延伸。 集成电路至少部分地通过互连层或导电通孔与封装表面上的I / O焊盘电耦合。 在特定实施例中，封装可以包括热管，散热器，多个集成电路，互连层，电连接封装和/或无源器件的不同部件的导电通孔。 在一些具体实施方案中，电介质层由合适的环氧树脂如SU-8型形成。 在本发明的方法方面，电介质层可以使用旋涂方法形成，并使用传统的光刻技术进行图案化。

公开(公告)号：US20100295638A1

公开(公告)日：2010-11-25

申请号：US12852743

申请日：2010-08-09

申请人： Peter J. Hopper ,  Trevor Niblock ,  Peter Johnson ,  Vladislav Vashchenko

发明人： Peter J. Hopper ,  Trevor Niblock ,  Peter Johnson ,  Vladislav Vashchenko

IPC分类号： H01H51/22 ,  H01H36/00

CPC分类号： H02M3/34

摘要： A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.

摘要翻译： MEMS磁通开关被制造为铁磁芯。 芯包括中心悬臂，其被制造为可以以其机械和材料性质确定的共振频率振荡的自由梁。 中心悬臂由相关运动振荡器施加的脉冲移动，运动振荡器可以是磁性或电动执行器。