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    Memory Cells and Methods Of Forming Memory Cells
    155.
    发明申请
    Memory Cells and Methods Of Forming Memory Cells 审中-公开
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US20150249089A1

    公开(公告)日：2015-09-03

    申请号：US14712291

    申请日：2015-05-14

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

    IPC: H01L27/108 ,  H01L21/285 ,  H01L21/02

    CPC classification number: H01L27/10832 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/28525 ,  H01L27/10861 ,  H01L27/10873 ,  H01L29/945

    Abstract: A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.

    Abstract translation: 存储单元包括晶体管器件，其包括一对源极/漏极，包括沟道的主体以及可操作地邻近沟道的栅极结构。 存储单元包括电容器，该电容器包括一对在其间具有电容器电介质的电容器电极。 电容器电极之一是通道或电耦合到通道。 电容器电极中的另一个包括主体而不是通道的一部分。 还公开了方法。

    SEMICONDUCTOR DEVICES INCLUDING A RECESSED ACCESS DEVICE AND METHODS OF FORMING SAME
    156.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING A RECESSED ACCESS DEVICE AND METHODS OF FORMING SAME 有权
    包括接入设备的半导体器件及其形成方法

    公开(公告)号：US20150194430A1

    公开(公告)日：2015-07-09

    申请号：US14148402

    申请日：2014-01-06

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Mingtao Li ,  Haitao Liu ,  Deepak Chandra Pandey ,  Mark Fischer

    IPC: H01L27/108 ,  H01L29/66 ,  H01L27/105

    CPC classification number: H01L27/10879 ,  H01L27/1052 ,  H01L27/10891 ,  H01L29/66613 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7857

    Abstract: A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.

    Abstract translation: 一种半导体器件包括凹入的存取器件，其包括第一柱，第二柱，连接第一和第二柱的沟道区，以及设置在沟道区上的栅。 沟道区具有比第一柱和第二柱的宽度窄的宽度。 凹陷进入装置的阵列包括从基板突出的多个支柱和多个通道区域。 每个通道区域具有小于约10nm的宽度并且连接相邻的柱以形成多个无连接的凹入式接入设备。 一种形成至少一个凹陷进入装置的方法还包括在衬底上形成柱，形成至少与柱相连的沟道区，沟道区具有相对较窄的宽度，以及形成至少部分围绕沟道区的栅极 至少三面。

    Methods of forming a vertical transistor
    157.
    发明授权
    Methods of forming a vertical transistor 有权
    形成垂直晶体管的方法

    公开(公告)号：US09054216B2

    公开(公告)日：2015-06-09

    申请号：US14319201

    申请日：2014-06-30

    Applicant: Micron Technology, Inc.

    Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

    IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/66 ,  H01L29/417 ,  H01L27/11

    CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

    Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

    MEMORY DEVICE INCLUDING 2-TRANSISTOR MEMORY CELL STRUCTURE FOR NEURAL NETWORK
    159.
    发明申请
    MEMORY DEVICE INCLUDING 2-TRANSISTOR MEMORY CELL STRUCTURE FOR NEURAL NETWORK 有权

    公开(公告)号：US20250029638A1

    公开(公告)日：2025-01-23

    申请号：US18778321

    申请日：2024-07-19

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao

    IPC: G11C5/06 ,  H01L23/528 ,  H10B12/00

    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory cell and a second memory cell, each of the first and second memory cells including a first transistor including a first region and a first charge storage structure separated from the first region; a second transistor including a second region formed over the first charge storage structure; a first data line coupled to the first memory cell configured to provide a first sum based on current on the first data line during a memory operation; a second data line coupled to the second memory cell configured to provide a second sum based on current on the second data line during the memory operation; and an output circuit to provide output information based on values of the first and second sums.

    DEVICES INCLUDING VERTICAL TRANSISTORS
    160.
    发明公开
    DEVICES INCLUDING VERTICAL TRANSISTORS 审中-公开

    公开(公告)号：US20240363763A1

    公开(公告)日：2024-10-31

    申请号：US18771108

    申请日：2024-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

    IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/78696 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/823412 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/7869

    Abstract: A device comprises a vertical transistor and a shielding material comprising a conductive material having a P+ type conductivity. The vertical transistor includes an electrode, a dielectric material adjacent to the electrode, and a channel region adjacent to the dielectric material. The channel region comprises a composite structure including at least two semiconductor materials. Also disclosed is a device comprising a first electrically conductive line, vertical transistors overlying the first conductive line, a second electrically conductive line overlying the vertical transistors, and a shielding material positioned between the two adjacent vertical transistors. Each of the vertical transistors comprises a gate electrode, a gate dielectric material on opposite sides of the gate electrode, and a channel region comprising a composite structure including at least two oxide semiconductor materials. The gate dielectric material positions between the gate electrode and the channel region. The shielding material comprises an electrically conductive material.

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