公开(公告)号：US20030224663A1

公开(公告)日：2003-12-04

申请号：US10379835

申请日：2003-03-04

Applicant: JohnsTech International Corporation

Inventor： David A. Johnson ,  Eric V. Kline

IPC: H01R013/66

CPC classification number: H01R13/2464 ,  H01L23/64 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/57 ,  H01R13/2407 ,  H01R13/6464 ,  H01R13/6471 ,  H01R13/6473 ,  H01R13/6608 ,  H01R13/719 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/025 ,  H05K7/1092 ,  H05K2201/0792 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: An apparatus for providing a controlled impedance directly to predetermined contact elements within a socket, thereby reducing the nulldistortingnull nature of the electrical interconnection system. In an illustrative embodiment of the present invention, predetermined contacts of a socket may have a resistance, inductance, capacitance, or a combination thereof incorporated therein. In another illustrative embodiment, at least one active element(s) may also be incorporated into predefined contacts. In this manner, predefined contacts may nullprocessnull the corresponding signal in a predetermined manner, defined by the circuitry incorporated on the contact itself. Illustrative functions that may be performed include, but are not limited to, amplifying, analog-to-digital converting, digital-to-analog converting, predefined logic functions, or any other function that may be performed via a combination of active and/or passive elements including a microprocessor function.

Abstract translation: 一种用于将受控阻抗直接提供给插座内的预定接触元件的设备，由此降低了电互连系统的“变形”性质。 在本发明的说明性实施例中，插座的预定触点可以具有并入其中的电阻，电感，电容或其组合。 在另一说明性实施例中，至少一个有源元件也可以并入预定义的触点中。 以这种方式，预定义的触点可以以预定的方式“处理”对应的信号，由接合体本身所包含的电路定义。 可以执行的说明性功能包括但不限于放大模数转换，数模转换，预定义逻辑功能或可以通过有源和/或数字转换的组合来执行的任何其他功能， 无源元件包括微处理器功能。

公开(公告)号：US06528872B2

公开(公告)日：2003-03-04

申请号：US10127082

申请日：2002-04-19

Applicant: Nai-Shung Chang

Inventor： Nai-Shung Chang

IPC: H01L2352

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K1/0216 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/094 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A ball grid array packaging structure for sealing a silicon chip on a substrate is disclosed. The substrate includes a front wiring layer and a back wiring layer. The front wiring layer includes a plurality of inner power rings and an outer power ring. The inner power rings are attached and together they surround a central region where the silicon chip is attached. The inner power rings and the outer power ring have a substantially identical width and the outer power ring surrounds all the inner power rings. The back wiring layer has a large number of interface power balls and core power balls. The interface power balls may be further subdivided into groups of inner power balls, while each group of inner power balls corresponds and couples with one of the inner power rings of the front wiring layer. The core power balls connect with the outer power ring and surround the interface power balls.

公开(公告)号：US20020181214A1

公开(公告)日：2002-12-05

申请号：US09872122

申请日：2001-05-31

Inventor： Paul S. Levy ,  David Frame

IPC: H05K007/02

CPC classification number: H05K1/141 ,  H05K1/181 ,  H05K3/3447 ,  H05K2201/0792 ,  H05K2201/1034 ,  H05K2201/10484 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: A dual-sided circuit board module designed for an operating position that is not perpendicular to a system motherboard will be coupled to the motherboard by leads having at least two different lengths. Because leads of differing lengths have differing associated inductance, the operating characteristics of the leads and therefore the devices coupled to the leads will differ. In order to improve the operating characteristics of the module, integrated circuit packages are selected based on the inductive (and possibly other) qualities of the leads to which the respective packages are coupled. In one embodiment, leads having a larger inductance are coupled to integrated circuit (IC) packages having a smaller inductance and vice versa, which allows the inductive characteristics of the various components of the module to have more closely matching inductive characteristics than would otherwise be possible.

Abstract translation: 设计用于不垂直于系统主板的操作位置的双面电路板模块将通过具有至少两个不同长度的引线耦合到母板。 因为不同长度的引线具有不同的相关电感，所以引线的工作特性以及耦合到引线的器件的操作特性将不同。 为了提高模块的工作特性，集成电路封装是基于各个封装所耦合的引线的电感（也可能是其它）的质量来选择的。 在一个实施例中，具有较大电感的引线被耦合到具有较小电感的反馈的集成电路（IC）封装，这允许模块的各种部件的电感特性具有比否则可能更紧密匹配的感应特性 。

公开(公告)号：US20020153166A1

公开(公告)日：2002-10-24

申请号：US10072213

申请日：2002-02-07

Inventor： Nai-Shung Chang

IPC: H05K001/11

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K1/0216 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/094 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A conductive pad layout is implemented on a substrate for BGA packaging structure. The substrate has a top trace surface on which is attached a chip, and a bottom trace surface. The top trace surface includes a first contact pad, a second contact pad placed closer to the chip than the first contact pad, and a reference contact pad placed adjacent to the second contact pad. A first bonding wire connects the first contact pad to the chip, and second and third bonding wires of shorter length respectively connect the second contact pad and the reference contact pad to the chip. Thereby, critical signal can pass through the second bonding wire and second contact pad with reduced interference. A reference dummy ball pad is also placed adjacent to a ball pad corresponding to the second contact pad on a bottom trace surface of the substrate to reduce interference.

Abstract translation: 在用于BGA封装结构的基板上实施导电焊盘布局。 衬底具有顶部迹线表面，其上附着有芯片和底部迹线表面。 顶部迹线表面包括第一接触焊盘，比第一接触焊盘更靠近芯片放置的第二接触焊盘以及与第二接触焊盘相邻放置的参考接触焊盘。 第一接合线将第一接触焊盘连接到芯片，并且较短长度的第二和第三接合线将第二接触焊盘和参考接触焊盘连接到芯片。 因此，临界信号可以以较小的干扰通过第二接合线和第二接触垫。 参考虚拟球垫也放置在与衬底的底部迹线表面上的第二接触焊盘相对应的球垫附近，以减少干扰。

公开(公告)号：US06358094B1

公开(公告)日：2002-03-19

申请号：US09538698

申请日：2000-03-30

Applicant: Yakov Belopolsky ,  Jenn Tsao

Inventor： Yakov Belopolsky ,  Jenn Tsao

IPC: H01R2400

CPC classification number: H05K1/148 ,  H01R12/7082 ,  H01R12/7088 ,  H01R13/658 ,  H05K2201/0792 ,  H05K2201/097 ,  H05K2201/10272 ,  H05K2201/1028 ,  H05K2203/1572

Abstract: A low inductance power connector for reducing inductance in an electrical conductor is provided. An interface connector connects circuit boards together while reducing inductance and increasing current carrying capacity. The connector for connecting circuit boards comprises a first contact having a body, a first mating portion and a second mating portion, and a second contact having a body, a third mating portion and a fourth mating portion. The first and second mating portions are substantially parallel and disposed on opposite sides of the body of the first contact, and the third and fourth mating portions are substantially parallel and disposed on opposite sides of the body of the second contact.

Abstract translation: 提供了用于降低电导体中的电感的低电感电源连接器。 接口连接器将电路板连接在一起，同时减少电感和增加载流能力。 用于连接电路板的连接器包括具有主体，第一配合部分和第二配合部分的第一触点和具有主体，第三配合部分和第四配合部分的第二触点。 第一和第二配合部分基本上平行并且设置在第一接触件的主体的相对侧上，并且第三和第四配合部分基本上平行并且设置在第二接触件的主体的相对侧上。

公开(公告)号：US6137061A

公开(公告)日：2000-10-24

申请号：US904526

申请日：1997-08-01

Applicant: Luis A. Aponte ,  Mark Benda ,  Joseph Peter Savicki

Inventor： Luis A. Aponte ,  Mark Benda ,  Joseph Peter Savicki

IPC: H01R24/44 ,  H01R24/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K3/42 ,  H05K1/16

CPC classification number: H01R24/50 ,  H05K1/024 ,  H05K1/115 ,  H01R2103/00 ,  H01R24/44 ,  H05K2201/0187 ,  H05K2201/0792 ,  H05K2201/09036 ,  H05K2201/09809 ,  H05K2201/10189 ,  H05K3/3447 ,  H05K3/42

Abstract: A printed circuit board that reduces parasitic effects on devices mounted thereon. The printed circuit board comprises a top layer and a bottom layer of a first insulating material having a first dielectric constant. The layers are configured to form holes whereby each of the holes has a first part extending through the top layer and a second part extending through the bottom layer. The bottom layer is further configured to comprise a second insulating material having a second dielectric constant, which second insulating material surrounds the second part of the hole. The devices mounted onto the printed circuit board have pins that extend through the holes. When the second dielectric constant is less than the first dielectric constant, the parasitic effects on the pins of the mounted devices are reduced.

Abstract translation: 一种减少对其上安装的装置的寄生效应的印刷电路板。 印刷电路板包括具有第一介电常数的第一绝缘材料的顶层和底层。 这些层被构造成形成孔，由此每个孔具有延伸穿过顶层的第一部分和延伸穿过底层的第二部分。 底层进一步构造成包括具有第二介电常数的第二绝缘材料，该第二绝缘材料围绕孔的第二部分。 安装到印刷电路板上的器件具有延伸穿过孔的引脚。 当第二介电常数小于第一介电常数时，对安装的器件的引脚的寄生效应降低。

公开(公告)号：US6087920A

公开(公告)日：2000-07-11

申请号：US798636

申请日：1997-02-11

Applicant: Igor Abramov

Inventor： Igor Abramov

IPC: H01F17/04 ,  H01F17/00 ,  H01F27/29 ,  H05K1/02 ,  H05K3/34 ,  H01F27/30

CPC classification number: H01F27/292 ,  H01F17/0033 ,  H05K3/3442 ,  H05K1/0233 ,  H05K2201/0792 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10583 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4902

Abstract: A monolithic inductor (10) comprises an elongated substrate having opposite distal ends (14) and (16), each end having an end cap extending from the opposite ends to support the substrate (12) in spaced relation from a PC board, the end caps being formed with non-mounting areas and a deflection area for preventing the substrate resting on the non-mounting area, a substantially steep side wall (16) on the substrate side of the end cap (14) at the non-mounting area, and an inclined ramp extending up to a top of the end cap on the substrate side substantially opposite the non-mounting area, an electrically conductive soldering band (30) extending partially around each end cap, each soldering band having a gap (34) at the non-mounting area for thereby reducing parasitic conduction in the band (30), and an electrically conductive layer formed on the substrate in a helical path extending between the opposite ends and in electrical contact with the conductive soldering bands (30) at the ramps (120).

Abstract translation: 单片电感器（10）包括具有相对的远端（14）和（16）的细长衬底，每个端部具有从相对端延伸的端盖，以与PC板隔开的关系支撑衬底（12），端部 盖子形成有非安装区域和用于防止基板搁置在非安装区域上的偏转区域，在非安装区域处在端盖（14）的基板侧上的基本上陡峭的侧壁（16） 以及一个倾斜的斜坡，其基本上与所述非安装区域相对地延伸到所述端盖的顶部的顶部;导电焊接带（30），其部分地围绕每个端盖延伸，每个焊带具有间隙（34） 所述非安装区域由此减小所述带（30）中的寄生传导，以及形成在所述基板上的螺旋形路径中的导电层，所述导电层在所述相对端之间延伸并在所述斜面处与所述导电焊带（30）电接触 （120）。

公开(公告)号：US5967848A

公开(公告)日：1999-10-19

申请号：US962924

申请日：1997-10-27

Applicant: David A. Johnson ,  Eric V. Kline

Inventor： David A. Johnson ,  Eric V. Kline

IPC: H01L23/64 ,  H01R12/57 ,  H01R13/24 ,  H01R13/646 ,  H01R13/6464 ,  H01R13/6471 ,  H01R13/6473 ,  H01R13/66 ,  H01R13/719 ,  H01R33/76 ,  H01R33/945 ,  H05K1/02 ,  H05K7/10 ,  H01R9/09

CPC classification number: H01R13/2464 ,  H01L23/64 ,  H01L23/642 ,  H01R13/2407 ,  H01R13/6464 ,  H01R13/6608 ,  H01R13/719 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/025 ,  H05K7/1092 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/57 ,  H01R13/6471 ,  H01R13/6473 ,  H05K2201/0792 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611

Abstract: An apparatus for providing a controlled impedance directly to predetermined contact elements within a socket, thereby reducing the "distorting" nature of the electrical interconnection system. In an illustrative embodiment of the present invention, predetermined contacts of a socket may have a resistance, inductance, capacitance, or a combination thereof incorporated therein. In another illustrative embodiment, at least one active element(s) may also be incorporated into predefined contacts. In this manner, predefined contacts may "process" the corresponding signal in a predetermined manner, defined by the circuitry incorporated on the contact itself. Illustrative functions that may be performed include, but are not limited to, amplifying, analog-to-digital converting, digital-to-analog converting, predefined logic functions, or any other function that may be performed via a combination of active and/or passive elements including a microprocessor function.

公开(公告)号：US5841075A

公开(公告)日：1998-11-24

申请号：US14885

申请日：1998-01-28

Applicant: David A. Hanson

Inventor： David A. Hanson

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/11 ,  H05K1/00

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/66 ,  H05K1/115 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09627 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

公开(公告)号：US5731960A

公开(公告)日：1998-03-24

申请号：US716842

申请日：1996-09-19

Applicant: Laurie P. Fung

Inventor： Laurie P. Fung

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K1/18

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K1/114 ,  H05K1/115 ,  H05K2201/0792 ,  H05K2201/0979 ,  H05K2201/10636 ,  H05K3/3452 ,  Y02P70/611

Abstract: A noise suppression apparatus for a printed circuit board (PCB) having two PCB pad regions, each containing a boundary pad region and a mounting pad region, wherein both boundary pad regions contain via connections. A decoupling capacitor is coupled to both mounting pad regions. Both boundary pad regions are solder mask except the mounting pad regions and the via connections.

Abstract translation: 一种用于具有两个PCB焊盘区域的印刷电路板（PCB）的噪声抑制装置，每个PCB焊盘区域包含边界焊盘区域和安装焊盘区域，其中两个边界焊盘区域都包含通孔连接。 去耦电容耦合到两个安装焊盘区域。 两个边界焊盘区域都是除了安装焊盘区域和通孔连接之外的焊接掩模。