公开(公告)号：US11056373B2

公开(公告)日：2021-07-06

申请号：US14918189

申请日：2015-10-20

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L25/03 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498

Abstract: Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

公开(公告)号：US10943869B2

公开(公告)日：2021-03-09

申请号：US15817054

申请日：2017-11-17

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L25/00 ,  H01L23/16 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

公开(公告)号：US10685948B1

公开(公告)日：2020-06-16

申请号：US16204679

申请日：2018-11-29

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/52 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00

Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.

公开(公告)号：US20200176419A1

公开(公告)日：2020-06-04

申请号：US16503806

申请日：2019-07-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip including a reconstituted chip-level back endo of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US10468381B2

公开(公告)日：2019-11-05

申请号：US14601623

申请日：2015-01-21

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065 ,  H01L25/00 ,  H01L49/02 ,  H01L23/528 ,  H01L21/78 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/16 ,  H01L23/498 ,  H01L23/50 ,  H01G4/40

Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.

公开(公告)号：US20180092213A1

公开(公告)日：2018-03-29

申请号：US15710579

申请日：2017-09-20

Applicant: Apple Inc.

Inventor： Corey S. Provencher ,  Meng Chi Lee ,  Derek J. Walters ,  Ian A. Spraggs ,  Flynn P. Carson ,  Shakti S. Chauhan ,  Daniel W. Jarvis ,  David A. Pakula ,  Jun Zhai ,  Michael V. Yeh ,  Alex J. Crumlin ,  Dennis R. Pyper ,  Amir Salehi ,  Vu T. Vo ,  Gregory N. Stephens

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K1/181 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/115 ,  H05K1/144 ,  H05K3/0014 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10674 ,  H05K2203/1316 ,  Y02P70/611

Abstract: The present disclosure is related to printed circuit board packages and methods of assembly that may be used in the fabrication of electrical devices. Printed circuit board packages may be manufactured by stacking printed circuit board assemblies. Each printed circuit board assembly may have multiple printed circuit boards supported by a resin mold. The printed circuit board assemblies may be shaped to improve space utilization efficiency and to accommodate large electrical components that are attached to the printed circuit board package.

公开(公告)号：US09847284B2

公开(公告)日：2017-12-19

申请号：US13753027

申请日：2013-01-29

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L25/03 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/498 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/03 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die.

公开(公告)号：US20170323883A1

公开(公告)日：2017-11-09

申请号：US15658670

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/06 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L21/77 ,  H01L49/02

CPC classification number: H01L27/0641 ,  H01L21/77 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

公开(公告)号：US09679801B2

公开(公告)日：2017-06-13

申请号：US14730171

申请日：2015-06-03

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Jun Zhai ,  Kunzhong Hu ,  Flynn P. Carson

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/768 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.

公开(公告)号：US20170141116A1

公开(公告)日：2017-05-18

申请号：US15420572

申请日：2017-01-31

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L27/10 ,  H01L23/498 ,  H01L25/18 ,  H01L49/02 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/64

CPC classification number: H01L27/101 ,  H01G4/228 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.