公开(公告)号：US09933493B2

公开(公告)日：2018-04-03

申请号：US15202065

申请日：2016-07-05

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yi-shing Lin

IPC: H02J7/00 ,  G01R31/36

CPC classification number: G01R31/3658 ,  G01R31/3606

Abstract: A battery management system for a battery pack including a plurality of battery cells connected in series is provided. The battery management system includes a first switching unit coupled to an anode of a first battery cell of the battery pack, having a first P-type transistor coupled to the anode of the first battery cell, a first resistor coupled between the anode of the first battery cell and a gate of the first P-type transistor, and a current mirror coupled to the gate of the first P-type transistor and the first resistor, draining a first mirror current from the first resistor in response to a control signal, so as to turn on the first P-type transistor. The system further includes a detection circuit coupled to the first switching unit.

公开(公告)号：US09911008B2

公开(公告)日：2018-03-06

申请号：US14884547

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/72 ,  G06F9/30 ,  H04L9/08 ,  G06F21/74 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/60 ,  G06F21/71 ,  H04L9/06

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0827 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor is provided in which an encrypted program can replace the decryption keys that are used to decrypt sections of the encrypted program. The microprocessor may be decrypting and executing a first section of the encrypted program when it encounters, decrypts, and executes an encrypted store-key instruction to store a new set of decryption keys. After executing the store-key instruction, the microprocessor decrypts and executes a subsequent section of the encrypted program using the new set of decryption keys. On-the-fly key switching may occur numerous times with successive encrypted store-key instructions and successive sets of encrypted instructions.

公开(公告)号：US09898303B2

公开(公告)日：2018-02-20

申请号：US14281585

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F12/08 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

公开(公告)号：US20180039584A1

公开(公告)日：2018-02-08

申请号：US15631154

申请日：2017-06-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Tze-Shiang WANG

IPC: G06F13/10 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F13/105 ,  G06F13/4022 ,  G06F13/4045 ,  G11B33/126

Abstract: A bridge device including a first connector, a first transceiver, a second connector, a second transceiver, a voltage processor, and a controller is provided. The first connector is configured to couple to a host and includes a first pin. The first transceiver is coupled between the first pin and a node and includes a first current limiter. The second connector is configured to couple to a peripheral device and includes a second pin. The second transceiver is coupled between the node and the second pin and includes a second current limiter. The voltage processor processes the voltage of the node to generate an operation voltage. The controller receives the operation voltage to determine whether to turn on at least one of the first and second transceivers.

公开(公告)号：US09829945B2

公开(公告)日：2017-11-28

申请号：US14980209

申请日：2015-12-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Darius D. Gaskins

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/24 ,  G06F13/36 ,  G06F15/163 ,  G06F9/30 ,  G06F9/50 ,  G06F9/445 ,  G06F15/82 ,  G06F11/36 ,  G06F11/14

CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

Abstract: A multi-die package for a microprocessor provides a power management synchronization system. The package has a plurality of dies. Each die has a plurality of cores, including a single master core. A plurality of sideband non-system-bus inter-die communication wires communicatively couple the dies to each other for a purpose of synchronizing power management. The master core of each die is configured to use one and only one of the inter-die communication wires to transmit power management synchronization messages to each of the other master cores. The master core of each die is also configured to receive power management synchronization messages from each of the other master cores via one or more inter-die communication wires. The cores use this system of inter-die communication wires to synchronize management of resources that affect both the performance and power consumption of the cores.

公开(公告)号：US09805198B2

公开(公告)日：2017-10-31

申请号：US15380063

申请日：2016-12-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57 ,  G06F9/44 ,  H04L29/06 ,  G06F13/24 ,  G06F13/42 ,  H04L9/32

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F13/24 ,  G06F13/4282 ,  G06F21/554 ,  G06F2221/2107 ,  H04L9/06 ,  H04L9/0618 ,  H04L9/0869 ,  H04L9/3231 ,  H04L9/3242 ,  H04L63/0435 ,  H04L63/0876 ,  H04L63/123

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a PCI Express access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

公开(公告)号：US09792121B2

公开(公告)日：2017-10-17

申请号：US14066520

申请日：2013-10-29

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Terry Parks ,  G. Glenn Henry

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3836

Abstract: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.

公开(公告)号：US20170285989A1

公开(公告)日：2017-10-05

申请号：US15193126

申请日：2016-06-27

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F3/0625 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F3/0634 ,  G06F3/0679 ,  G06F3/0688 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/154 ,  Y02D10/171 ,  Y02D50/20

Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.

公开(公告)号：US20170277589A1

公开(公告)日：2017-09-28

申请号：US15221598

申请日：2016-07-28

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F11/10 ,  H03M13/11 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/1105 ,  H03M13/1128

Abstract: A non-volatile memory (NVM) apparatus and an empty page detection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller reads the content of a memory page of the NVM. The controller performs Low Density Parity Check (LDPC) decoding for at least one codeword of the memory page to obtain a decoded codeword and a check-result vector. The controller determines that the memory page is not an empty page when the LDPC decoding for the codeword is successful. The controller counts an amount of the bits being 1 (or 0) in the check-result vector when the LDPC decoding for the codeword is fail. Based on the amount of the bits being 1 (or 0) in the check-result vector, the controller determines whether the memory page is an empty page.

公开(公告)号：US20170277472A1

公开(公告)日：2017-09-28

申请号：US15166272

申请日：2016-05-27

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Huei Huang ,  Yi-Lin Lai

IPC: G06F3/06 ,  G06F11/07 ,  G06F12/10

CPC classification number: G06F12/1009 ,  G06F3/0616 ,  G06F3/0649 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1048 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7204

Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned with a group age parameter. The adjusting of the group age parameters is triggered by a writing instruction of a host. When an age parameter of the group age parameters exceeds a predetermined range, the controller performs a scanning operation to the non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the age parameter, so as to check an error-bit quantity. The controller decides whether the storage block data-moving operation is performed to the non-volatile storage block corresponding to the corresponding logical block address group based on the results of the scanning operation.