公开(公告)号：US10403733B2

公开(公告)日：2019-09-03

申请号：US15776752

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Van H. Le ,  Matthew V. Metz ,  Willy Rachmady ,  Jack T. Kavalieros ,  Rafael Rios

IPC: H01L29/76 ,  H01L29/51 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190189749A1

公开(公告)日：2019-06-20

申请号：US16326890

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Van Le ,  Seung Hoon Sung ,  Jack Kavalieros ,  Ashish Agrawal ,  Harold Kennel ,  Siddharth Chouksey ,  Anand Murthy ,  Tahir Ghani ,  Glenn Glass ,  Cheng-Ying Huang

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L29/1079 ,  H01L21/26506 ,  H01L29/16 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66 ,  H01L29/7851

Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

公开(公告)号：US10236369B2

公开(公告)日：2019-03-19

申请号：US15790907

申请日：2017-10-23

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

IPC: H01L29/775 ,  B82Y10/00 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778 ,  H01L21/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/15 ,  H01L29/51 ,  H01L29/165

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US10229991B2

公开(公告)日：2019-03-12

申请号：US15505911

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L29/06

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US10181518B2

公开(公告)日：2019-01-15

申请号：US15464888

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Niti Goel ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/205 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US10177249B2

公开(公告)日：2019-01-08

申请号：US15644488

申请日：2017-07-07

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/778 ,  H01L29/775 ,  H01L29/417 ,  H01L29/15 ,  H01L29/201 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

公开(公告)号：US10096682B2

公开(公告)日：2018-10-09

申请号：US15464931

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sherry Taft ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L27/108 ,  H01L29/20 ,  H01L21/02 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8258

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

公开(公告)号：US10096474B2

公开(公告)日：2018-10-09

申请号：US15604550

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Niloy Mukherjee ,  Niti Goel ,  Sanaz K. Gardner ,  Pragyansri Pathi ,  Matthew V. Metz ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  James M. Powers ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: G06Q30/02 ,  H01L21/02 ,  H01L21/762 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/267 ,  H01L29/165 ,  H01L21/8258 ,  H01L27/092

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

公开(公告)号：US10032911B2

公开(公告)日：2018-07-24

申请号：US15499794

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert S. Chau ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz Gardner ,  Ravi Pillarisetty

IPC: H01L29/20 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/205 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/34

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

公开(公告)号：US09972686B2

公开(公告)日：2018-05-15

申请号：US15121745

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Willy Rachmady ,  Roza Kotlyar ,  Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros

IPC: H01L21/70 ,  H01L29/161 ,  H01L27/11 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.